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| PRELIMINARY DATA SHEET MICRONAS INTERMETALL MSP 3400 C Multistandard Sound Processor MICRONAS Edition Dec. 8, 1997 6251-377-3PD MSP 3400C Contents Page 5 6 6 6 6 7 7 9 9 9 9 10 10 10 10 10 10 11 11 11 13 13 14 15 16 17 18 18 18 18 18 19 20 20 21 21 23 24 24 26 Section 1. 2. 2.1. 2.2. 2.3. 3. 3.1. 4. 4.1. 4.1.1. 4.1.2. 4.1.3. 4.1.4. 4.1.5. 4.1.6. 4.1.7. 4.1.8. 4.2. 4.3. 4.3.1. 4.4. 4.5. 4.6. 4.7. 5. 5.1. 5.2. 5.2.1. 5.2.2. 5.2.3. 5.2.4. 5.3. 6. 6.1. 6.2. 6.2.1. 6.2.2. 6.2.3. 6.2.4. 6.2.5. Title Introduction Features of the MSP 3400C Features of the Demodulator and Decoder Sections Features of the DSP-Section Features of the Analog Section Application Fields of the MSP 3400C German 2-Carrier System (DUAL FM System) Architecture of the MSP 3400C Demodulator Block Analog Sound IF - Input Section Quadrature Mixers Lowpass Filtering Block for Mixed Sound IF Signals Phase and AM Discrimination Differentiators Lowpass Filter Block for Demodulated Signals High Deviation FM Mode MSPC-Mute Function in the Dual Carrier FM Mode Analog Section and SCART Switching Facilities MSP 3400C Audio Baseband Processing Dual Carrier FM Stereo/Bilingual Detection Audio PLL and Crystal Specifications ADR Bus S-Bus Interface I2S Bus Interface I2C Bus Interface: Device and Subaddresses Protocol Description Proposal for MSP 3400C I2C Telegrams Symbols Write Telegrams Read Telegrams Examples Start Up Sequence Programming the Demodulator Part Registers: Table and Addresses Registers: Functions and Values Setting of Parameter AD_CV Control Register `MODE_REG' FIR-Filter Switches FIR-Parameter DCO-Increments PRELIMINARY DATA SHEET 2 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C Contents, continued Page 27 27 27 28 28 28 29 29 31 32 33 33 34 34 35 35 36 36 36 37 37 37 37 37 38 38 38 38 39 39 40 40 41 41 41 42 42 42 42 42 Section 6.3. 6.4. 6.4.1. 6.4.2. 6.4.3. 6.4.4. 7. 7.1. 7.1.1. 7.1.2. 7.1.3. 7.1.4. 7.1.5. 7.1.6. 7.1.7. 7.1.8. 7.1.9. 7.1.10. 7.1.11. 7.1.12. 7.1.13. 7.1.14. 7.1.15. 7.1.16. 7.1.17. 7.1.18. 7.1.19. 7.1.20. 7.1.21. 7.1.22. 7.1.23. 7.2. 7.3. 7.3.1. 7.3.2. 7.3.3. 7.3.4. 7.3.5. 7.3.6. 7.3.7. Title Sequences to Transmit Parameters and to Start Processing Software Proposals for Multistandard TV-Sets Multistandard System B/G German DUAL FM Satellite Mode Automatic Search Function for FM-Carrier Detection Automatic Standard Detection Programming the Audio Processing Part Summary of the DSP Control Registers Volume Loudspeaker Channel and Headphone Channel Balance Loudspeaker and Headphone Channel Bass Loudspeaker and Headphone Channel Treble Loudspeaker and Headphone Channel Loudness Loudspeaker and Headphone Channel Spatial Effects Loudspeaker Channel Volume SCART Channel Source Modes Channel Matrix Modes SCART Prescale FM Prescale FM Matrix Modes FM Fixed Deemphasis FM Adaptive Deemphasis I2S1 and I2S2 Prescale ACB Register, Definition of the SCART-Switches and DIG_CTR_OUT Pins Beeper Identification Mode FM DC Notch Mode Tone Control Equalizer Loudspeaker Channel Automatic Volume Correction (AVC) Subwoofer on Headphone Output Exclusions Summary of Readable Registers Stereo Detection Register Quasi Peak Detector DC Level Register MSP Hardware Version Code MSP Major Revision Code MSP Product Code MSP ROM Version Code MICRONAS INTERMETALL 3 MSP 3400C Contents, continued Page 43 43 44 48 51 53 53 54 58 64 65 67 67 68 69 69 Section 8. 8.1. 8.2. 8.3. 8.4. 8.5. 8.5.1. 8.5.2. 8.5.3. 9. 10. 11. 12. 13. 14. 15. Title Specifications Outline Dimensions Pin Connections and Descriptions Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics Application of the MSP 3400C DMA Application MSP Application with External Clock ADR Application PRELIMINARY DATA SHEET I2S Bus in Master/Slave Configuration with Standby Mode APPENDIX A: Technical Code History APPENDIX B: Documentation History 4 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C sound IF signal-in, down to processed analog AF-out, is performed in a single chip. The IC is produced in 0.8 m CMOS technology, combined with high performance digital signal processing. The MSP 3400C 0.8 CMOS version is fully pin and software compatible to the 1.0 MSP 3400 and MSP 3410. The main difference between the MSP 3400C and the MSP 3410, consists of the MSP 3410 being able to decode NICAM signals. The MSP 3400C is available in PLCC68, PSDIP64, PSDIP52, and PQFP80 package. Note: To achieve compatibility with the functions of MSP 3400 and MSP 3410 (except NICAM), the load sequences must be programmed as described in the data sheet of MSP 3410. Multistandard Sound Processor Release Notes: The hardware description in this document is valid for the MSP 3400C - C8 and newer codes. Revision bars indicate significant changes to the previous version. 1. Introduction The MSP 3400C is designed as single-chip Multistandard Sound Processor for applications in analog and digital TV sets, satellite receivers and video recorders. The MSP-family, which is based on the MSP 2400, demonstrates the progressive development towards highly integrated multi-functional ICs. The MSP 3400C, again, improves function integration: The full TV sound processing, starting with analog MSP 3400C Integrated Functions: - FM-demodulation of all terrestrial standards (incl. identification decoding) - FM-demodulation of all satellite standards - various deemphasis types (incl. Panda1) - volume, balance, bass, treble, loudness for loudspeaker and headphone output - automatic volume correction (A.V.C.) - 5 band graphic equalizer - subwoofer output alternatively with headphone output - spatial effect (pseudostereo/basewidth enlargement) - ADR together with DRP 3510 A - Dolby ProLogic together with DPL 3418/19/20 A - 3 pairs of D/A converters - 1 pair of A/D converters - SCART switches ADR/SBus I2S 3 Sound IF 1 Sound IF 2 5 I2C 2 2 2 LOUDSPEAKER OUT HEADPHONE OUT SCART1 OUT SCART2 OUT MONO IN SCART1 IN SCART2 IN SCART3 IN 2 2 2 MSP 3400C 2 2 Fig. 1-1: Main I/O Signals MSP 3400C MICRONAS INTERMETALL 5 MSP 3400C 2. Features of the MSP 3400C 2.1. Features of the Demodulator and Decoder Sections The MSP 3400C is designed to perform demodulation of FM-mono TV sound and two carrier FM systems according to the German or Korean terrestrial specs. With certain constraints, it is also possible to do AM-demodulation according to the SECAM system. Alternatively, the satellite specs can be processed with the MSP 3400C. For FM carrier detection in satellite operation, the AMdemodulation offers a powerful feature to calculate the carrier field strength, which can be used for automatic search algorithms. So, the IC facilitates a first step towards multistandard capability with its very flexible application and may be used in TV-sets, satellite tuners, and video recorders. The MSP 3400C facilitates profitable multistandard capability, offering the following advantages: - two selectable analog inputs (TV and SAT-IF sources) - Automatic Gain Control (AGC) for analog input: input range: 0.14 - 3 Vpp - integrated A/D converter for sound-IF inputs - all demodulation and filtering is performed on chip and is individually programmable - no external filter hardware is required - only one crystal clock (18.432 MHz) is necessary - FM carrier level calculation for automatic search algorithms and carrier mute function - high deviation FM-mono mode (max. deviation: approx. $360 kHz) PRELIMINARY DATA SHEET 2.2. Features of the DSP-Section - flexible selection of audio sources to be processed - digital input and output interfaces via I2S-Bus for external DSP-processors, surround sound, ADR etc. - digital interface to process ADR (Astra Digital Radio) together with DRP 3510 A - performance of all deemphasis systems including adaptive Wegener Panda 1 without external components or controlling - digitally performed FM-identification decoding and dematrixing - digital baseband processing: volume, bass, treble, 5-band equalizer, loudness, pseudostereo, and basewidth enlargement - simple controlling of volume, bass, treble, equalizer etc. - increased audio bandwidth for FM-Audio-signals (20 Hz - 15 kHz, $1 dB) 2.3. Features of the Analog Section - three selectable analog pairs of audio baseband inputs (= three SCART inputs) input level: 2 V RMS, input impedance: 25 k - one selectable analog mono input (i.e. AM sound), input level: 2 V RMS, input impedance: 10 k - two high quality A/D converters, S/N-Ratio: 85 dB - 20 Hz to 20 kHz Bandwidth for SCART-to-SCARTCopy facilities - MAIN (loudspeaker) and AUX (headphones): two pairs of 4-fold oversampled D/A-converters output level per channel: max. 1.4 V RMS output resistance: max. 5 k S/N-Ratio: 85 dB at maximum volume max. noise voltage in mute mode: 10 V (BW: 20 Hz ...16 kHz) - one pair of four-fold oversampled D/A-converters supplying two selectable pairs of SCART-Outputs. Output level per channel: max. 2 V RMS, output resistance: max. 0.5 k, S/N-Ratio: 85 dB (20 Hz...16 kHz) 6 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 3.1. German 2-Carrier System (DUAL FM System) Since September 1981, stereo and dual sound programs have been transmitted in Germany using the 2-carrier system. Sound transmission consists of the already existing first sound carrier and a second sound carrier additionally containing an identification signal. More details of this standard are given in Table 3-1. 3. Application Fields of the MSP 3400C The MSP 3400C processes TV sound according to the German and Korean two carrier system and the commonly used satellite systems. In the following sections, a brief overview on the German FM-Stereo system shows what is required of a multistandard audio IC. Table 3-1: European TV standards TV-System B/G B/G L I D/K Position of Sound Carrier /MHz 5.5/5.7421875 5.5/5.85 6.5/5.85 6.0/6.552 6.5 /6.2578125 D/K1 6.5/6.7421875 D/K2 6.5/5.85 D/K-NICAM 4.5 4.5/4.724212 6.5 7.02/7.2 Sound Modulation FM-Stereo FM-Mono/NICAM AM-Mono/NICAM FM-Mono/NICAM FM-Stereo FM-Mono/NICAM FM-Mono FM-Stereo FM-Mono FM-Stereo NTSC PAL PAL Color System PAL PAL SECAM-L PAL SECAM-East Country Germany Scandinavia,Spain France UK USSR Hungary USA Korea Europe (ASTRA) Europe (ASTRA) M M-Korea Satellite Satellite 33 34 39 MHz 5 9 MHz SAW Filter Sound IF Mixer Sound IF Filter Tuner Loudspeaker Vision Demodulator AM Sound MSP 3400C SCART1 2 2 2 2 2 Headphone SCART1 SCART2 Composite Video SCART Inputs SCART Outputs SCART2 SCART3 According to the mixing characteristics of the Sound-IF-mixer, the Sound-IF filter may be omitted. Fig. 3-1: Typical MSP 3400C application MICRONAS INTERMETALL I 2S optional Feature Processor I 2S SBUS / ADR AMU and DMA or DRP 7 MSP 3400C Table 3-2: Key parameters for B/G, D/K, and M 2-carrier sound system Sound Carriers Carrier FM1 B/G Vision/sound power difference Sound bandwidth Pre-emphasis Frequency deviation Sound Signal Components Mono transmission Stereo transmission Dual sound transmission mono (L+R)/2 language A (L+R)/2 50 s 50 kHz D/K 13 dB 40 Hz to 15 kHz 75 s 25 kHz M PRELIMINARY DATA SHEET Carrier FM2 B/G D/K 20 dB M 50 s 50 kHz 75 s 25 kHz mono R language B (L-R)/2 Identification of Transmission Mode on Carrier FM2 Pilot carrier frequency in kHz Type of modulation Modulation depth Modulation frequency 54.6875 AM 50% mono: unmodulated stereo: 117.5 Hz dual: 274.1 Hz 149.9 Hz 276.0 Hz 55.0699 Note: NICAM decoding can be achieved by using the MSP 3410 instead of the MSP 3400C. Since the MSP 3400C and the MSP 3410 are fully pin and software downwards compatible (concerning all features of MSP 3410), it is possible to decide in the assembly line, whether the application should be able to decode NICAM or not. 8 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C Some combinations of SAW filters and sound IF mixer ICs, however, show large picture components on their outputs. In this case, filtering is recommended. It was found that the high pass filters formed by the coupling capacitors at pins ANA_IN1+ and ANA_IN2+ as shown in the application diagram are sufficient in most cases. 4. Architecture of the MSP 3400C Fig. 4-1 shows a simplified block diagram of the IC. Its architecture is split into three functional blocks: 1. demodulator section 2. digital signal processing (DSP) section performing audio baseband processing 3. analog section containing two A/D-converters, 6 D/A-converters, and SCART switching facilities 4.1. Demodulator Block 4.1.1. Analog Sound IF - Input Section The input pins ANA_IN1+, ANA_IN2+, and ANA_IN- offer the possibility to connect two different sound IF sources to the MSP 3400C. By means of bit [8] of AD_CV (see Table 6-3), either terrestrial or satellite sound IF signals can be selected. The analog-to-digital conversion of the preselected sound IF signal is done by a flash-converter, whose output can be used to control an automatic gain circuit (AGC), providing optimum level for a wide range of input levels. It is possible to switch between automatic gain control and a fixed (setable) input gain. In the optimum case, the input range of the A/D converter is completely covered by the sound IF source. 4.1.2. Quadrature Mixers The digital input coming from the integrated A/D converter may contain audio information at a frequency range of theoretically 0 to 9 MHz corresponding to the selected standards. By means of two programmable quadrature mixers two different audio sources, for example FM1 and FM2, may be shifted into baseband position. In the following, the two main channels are provided to process either: - FM mono (channel 2) or - FM2 (channel 1) and FM1 (channel 2). Two independent digital oscillators are provided to generate two pairs of sin/cos-functions. Two programmable increments, to be divided up into Low- and High Part, determine frequency of the oscillator, which corresponds to the frequency of the desired audio carrier. In section 6.1., format and values of the increments are listed. S_CL / ADR_CL S_DA_IN / ADR_DA S_ID / ADR_WS AUD_CL_OUT XTAL_OUT I2S_DA_OUT I2S_CL XTAL_IN I2S_WS I2S_DA_IN_1/2 SBUS/ADR Interface I2S Interface Audio PLL Sound IF ANA_IN1+ ANA_IN2+ S1..4 I2S1/2L/R I2SL/R LOUDSPEAKER L LOUDSPEAKER R Demodulator FM1 / AM FM2 D/A D/A DACM_L Loudspeaker DACM_R DFP Mono MONO_IN IDENT HEADPHONE L HEADPHONE R SCART_L D/A D/A DACA_L Headphone DACA_R SC1_IN_L SCART1 SC1_IN_R A/D A/D SC2_IN_L SCART2 SC2_IN_R SCART_R SCART_L SCART_R D/A D/A SC1_OUT_L SCART 1 SC1_OUT_R SC2_OUT_L SC3_IN_L SCART3 SC3_IN_R SCART Switching Facilities SCART 2 SC2_OUT_R Fig. 4-1: Architecture of the MSP 3400C MICRONAS INTERMETALL 9 MSP 3400C PRELIMINARY DATA SHEET DCO1 Oscillator FIR_REG_1 Phase Mixer VREFTOP Lowpass Phase and AM Discrimination Differentiator Mute Lowpass MODE_REG[8] ADR_DA FM2 MSPC sound IF channel 1 (MSP-CH1: FM2) AD_CV[7:1] ANA_IN1+ AGC ANA_IN2+ AD_CV[8] AD Amplitude Carrier Detect Mixer AD_CV[9,10,11] IDENT Carrier Detect ANA_IN- MSPC sound IF channel 2 (MSP-CH2: FM1, AM) Mixer Lowpass Amplitude Phase and AM Discrimination Phase Mute Differentiator MODE_REG[8] Lowpass FM1/AM FRAME Pins Internal signal lines Control registers FIR_REG_2 Oscillator FM2 DCO2 DCO2 Fig. 4-2: Demodulator architecture 4.1.3. Lowpass Filtering Block for Mixed Sound IF Signals FM bandwidth limitation is performed by a linear phase Finite Impulse Response (FIR-filter). Just like the oscillators' increments, the filter coefficients are programmable and are written into the IC by the CCU via the control bus. Two not necessarily different sets of coefficients are required, one for channel 1 (FM2) and one for channel 2 (FM1=FM-mono). In section 6.2.4., several coefficient sets are proposed. 4.1.4. Phase and AM Discrimination The filtered sound IF signals are demodulated by means of the phase and amplitude discriminator block. On the output, the phase and amplitude is available for further processing. AM signals are derived from the amplitude information, whereas the phase information serves for FM demodulation. 4.1.5. Differentiators FM demodulation is completed by differentiating the phase information output. 4.1.6. Lowpass Signals Filter Block for Demodulated cy of 32 kHz. The usable bandwidth of the final baseband signals is about 15 kHz. 4.1.7. High Deviation FM Mode By means of MODE_REG [9], the maximum FM-deviation can be extended to approximately $360 kHz. Since this mode can be applied only for the MSPC sound IF channel 2, the corresponding matrices in the baseband processing must be set to sound A. Apart from this, the coefficient sets 380 kHz FIR_REG2 or 500 kHz FIR_REG2 must be chosen for the FIR_REG_2. For a given deviation, in relation to the normal FM-mode, the audio level of the high-deviation mode is reduced by 6 dB. 4.1.8. MSPC-Mute Function in the Dual Carrier FM Mode To prevent noise effects or FM identification problems in the absence of one of the two FM carriers, the MSP 3400 C offers a carrier detection feature, which must be activated by means of AD_CV[9]. The mute level may be programmed by means of AD_CV[10,11]. (see section 6.2.1.) If no FM carrier is available at the MSPC channel 1, the corresponding channel FM2 is muted. If no FM carrier is available at the MSPC channel 2, the corresponding channel FM1 is muted. In case of the absence of both FM carriers, pure noise will be amplified by the input AGC. Therefore, a proper mute function depends on the noise quality of the TV set's IF part and cannot be guaranteed. The mute function is not recommended for the satellite mode. MICRONAS INTERMETALL The demodulated FM and AM signals are further lowpass filtered and decimated to a final sampling frequen10 PRELIMINARY DATA SHEET MSP 3400C 4.3. MSP 3400C Audio Baseband Processing By means of the DFP processor, all audio baseband functions are performed by digital signal processing (DSP). The DSP functions are grouped into three processing parts: input preprocessing, channel selection, and channel postprocessing. The input preprocessing is intended to prepare the various signals of all input sources in order to form a standardized signal at the input to the channel selector. The signals can be adjusted in volume, are processed with the appropriate deemphasis, and are dematrixed if necessary. Having prepared the signals that way, the channel selector makes it possible to distribute all possible source signals to the desired output channels. The ability to route in an external coprocessor for special effects like surround and sound field processing is of special importance. Routing can be done with each input source and output channel via the I2S inputs and outputs. All input and output signals can be processed simultaneously. Note that the NICAM input signals are only available in the MSP 3410 version. While processing the adaptive deemphasis, no dual carrier stereo (German or Korean) is possible. Identification values are not valid either. 4.3.1. Dual Carrier FM Stereo/Bilingual Detection In the German and Korean TV standard, audio information can be transmitted in three modes: mono, stereo, or bilingual. To obtain information about the current audio operation mode, the MSP 3400C detects the so-called identification signal. Information is supplied via the Stereo Detection Register to an external CCU. Stereo Detection Filter IDENT AM Demodulation Bilingual Detection Filter Level Detect 4.2. Analog Section and SCART Switching Facilities The analog input and output sections offer a wide range of switching facilities, which are shown in Fig. 4-3. To design a TV-set with 3 pairs of SCART-inputs and two pairs of SCART-outputs, no external switching hardware is required. The switches are controlled by the ACB bits defined in the audio processing interface (see section 7. Programming the Audio Processing Part). If the MSP 3400C is switched off by first pulling STANDBYQ low, and then disconnecting the 5 V, but keeping the 8 V power supply (`Standby'-mode), the switches S1, S2, and S3 maintain their position and function. This facilitates the copying from selected SCART-inputs to SCART-outputs in the TV-sets standby mode. SCART_IN SC1_IN_L/R MONO SC2_IN_L/R SC3_IN_L/R 2 2 2 2 ACB[1:0] 00 01 10 11 S1 A D 2 SCARTL/R to Audio Baseband Processing (DFP) ACB[3:2] 2 2 from Audio Baseband Processing (DFP) SCARTL/R D 2 A 2 11 S2 2 00 01 2 10 SC1_OUT_L/R SCART_OUT ACB[5:4] 2 2 2 00 01 10 S3 2 SC2_OUT_L/R Fig. 4-3: SCART-Switching Facilities Bold lines determine the default configuration Level Detect Stereo Detection Register - In case of power-on start or starting from standby, the IC switches automatically to the default configuration, shown in Fig. 4-3. This takes place after the first I2C transmission into the DFP part. By transmitting the ACB register first, the default setting mode can be changed. Fig. 4-4: Stereo/bilingual detection MICRONAS INTERMETALL 11 Channel Select 12 Analog Inputs SCARTL SCARTR SCART Prescale DC level readout FM1 FM1 Demodulated IF Inputs FM2 Deemphasis 50/75 s J17 FM FM-Matrix Prescale Headphone L Headphone Channel Matrix SBUS1 SBUS2 SBUS Inputs SBUS3 SBUS4 SCART Channel Matrix Volume SCART_L SCART_R SCART Outputs Bass/ Treble Beeper Loudspeaker Channel Matrix AVC Bass/ Treble or Equalizer MSP 3400C Loudness Complementary Highpass Spatial Effects Loudspeaker L Balance Loudspeaker R Level Adjust Volume Subwoofer Loudspeaker Outputs Lowpass Adaptive Deemphasis DC level readout FM2 Volume Loudness Balance Headphone R Headphone Outputs I 2S1L I 2S1R I 2S Bus Inputs I 2S2L I 2S2R I 2S1 Prescale I 2S2 Prescale I 2S Channel Matrix I 2SL I 2SR I 2S Outputs Quasi-PeakChannel Matrix Quasi peak readout L Quasi-Peak Detector Quasi peak readout R PRELIMINARY DATA SHEET MICRONAS INTERMETALL Fig. 4-5: Audio baseband processing (DSP-Firmware) PRELIMINARY DATA SHEET MSP 3400C Table 4-1: Several examples for recommended channel assignments for demodulator and audio processing part Mode B/G-Stereo B/G-Bilingual MSPC Sound IFChannel 1 / FM2 FM2 (5.74 MHz): R FM2 (5.74 MHz): Sound B MSPC Sound IFChannel 2 / FM1 FM1 (5.5 MHz): (L+R)/2 FM1 (5.5 MHz): Sound A FMMatrix B/G Stereo No Matrix Channel Select Speakers: FM Speakers: FM H.Phone : FM Speakers: FM Speakers: FM Speakers: FM H.Phone : FM Speakers: FM H.Phone : FM Channel Matrix Stereo Speakers: Sound A H.Phone : Sound B Sound A Stereo Speakers: Sound A H.Phone :Sound B=C Speakers: Sound A H.Phone : Sound A Sat-Mono Sat-Stereo Sat-Bilingual not used 7.20 MHz: R 7.38 MHz: Sound C FM (6.5 MHz): mono 7.02 MHz: L 7.02 MHz: Sound A No Matrix No Matrix No Matrix Sat High Dev. Mode (e.g. EutelSat) don't care 6.552 MHz No Matrix 4.4. Audio PLL and Crystal Specifications The MSP 3400C runs at 18.432 MHz. A detailed specification of the required crystal for different packages and master/slave applications can be found in Table 8.5.2. The clock supply of the entire system depends on the MSP 3400C operation mode: 1. FM-Stereo/I2S Master operation: The system clock runs free on the crystal's 18.432 MHz. 2. I2S Slave operation: In this case, the system clock is synchronizing on the I2S_WS signal, which is fed into the MSP 3400C (Mode_Reg[3] = 1). 3. D2-MAC operation: In this case, the system clock is locked to a synchronizing signal (DMA_SYNC) supplied by the D2-MAC chip (Mode_Reg[0] = 1). The DMA and the AMU chips can be driven by the MSP 3400C audio clock (AUD_CL_OUT). Remark on using the crystal: External capacitors at each crystal pin to ground are required. They are necessary for tuning the open-loop frequency of the internal PLL and for stabilizing the frequency in closed-loop operation. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match the center of the tolerance range between 18.433 and 18.431 MHz as closely as possible. Due to different layouts of customer PCBs, the matching capacitor size should be defined in the application (see also Table 8.5.2.). 4.5. ADR Bus To be able to process ADR, the MSPC has a special designed interface to work together with DRP 3510A. To be prepared for an upgrade to ADR with an additional DRP board, the following lines of MSP 3400C should be provided on a feature connector: - AUD_CL_OUT - I2S_DA_IN1 or I2S_DA_IN2 - I2S_DA_OUT - I2S_WS - I2S_CLK - S_CL = ADR_CL - S_ID = ADR_WS - S_DA_IN = ADR_DA MICRONAS INTERMETALL 13 MSP 3400C 4.6. S-Bus Interface Digital audio information provided by the DMA 2381 via the AMU is serially transmitted to the MSP 3400C via the S-Bus. The MSP 3400C is always in S-Bus master mode. The S-Bus interface consists of three pins: 1. S_DA_IN: Four channels (4*16 bits) per sampling cycle (32 kHz) are transmitted. 2. S_CL: Gives the timing for the transmission of S-DATA (4.608 MHz). 3. S_ID: After 64 S-CLOCK cycles, the S_ID determines the end of one sampling period. A detailed timing diagram is shown in Fig. 4-6. PRELIMINARY DATA SHEET (Data: MSB first) H S-Ident L H S-Clock L H S-Data L A B 16 Bit Sound 1 16 Bit Sound 2 16 Bit Sound 3 16 Bit Sound 4 64 Clock Cycles Section A H S-Ident L tS1 H S-Clock 4.608 MHz L tS4 H S-Data L LSB of Sound 1 tS5 tS2 Section B tS6 H S-Ident L tS3 H S-Clock 4.608 MHz L H S-Data L MSB of Sound 4 Fig. 4-6: S-Bus timing diagram 14 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C The I2S bus interface consists of five pins: 1. I2S_DA_IN1: For input, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted. 2. I2S_DA_IN2: For input, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted. 3. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted. 4. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024 MHz). 5. I2S_WS: The I2S_WS word strobe line defines the left and right sample. A detailed timing diagram is shown in Fig. 4-7. 4.7. I2S Bus Interface By means of this standardized interface, additional feature processors can be connected to the MSP 3400C. Two possible formats are supported: The standard mode (MODE_REG[4]=0) selects the SONY format, where the I2S_WS signal changes at the word boundaries. The so-called PHILIPS format, which is characterized by a change of the I2S_WS signal, one I2S_CL period before the word boundaries, is selected by setting MODE_REG[4]=1. The MSP 3400C normally serves as the master on the I2S interface. Here, the clock and word strobe lines are driven by the MSP 3400C. By setting MODE_REG[3]=1, the MSP 3400C is switched to a slave mode. Now, these lines are input to the MSP 3400 C, and the master clock is synchronized to 576 times the I2S_WS rate (32 kHz). No D2MAC operation is possible in this mode. (Data: MSB first) FI2SWS I2S_WS SONY Mode PHILIPS Mode PHILIPS/SONY Mode programmable by MODE_REG[4] I2S_CL Detail A I2S_DAIN R LSB L MSB SONY Mode PHILIPS Mode Detail C L LSB R MSB R LSB L LSB 16 bit left channel Detail B I2S_DAOUT R LSB L MSB L LSB R MSB 16 bit right channel R LSB L LSB 16 bit left channel 16 bit right channel Detail C I2S_CL FI2SCL Detail A,B I2S_CL TI2SWS1 TI2SWS2 TI2S1 TI2S2 I2S_WS as INPUT TI2S5 TI2S6 I2S_DA_IN TI2S3 TI2S4 I2S_WS as OUTPUT I2S_DA_OUT Fig. 4-7: I2S Bus timing diagram MICRONAS INTERMETALL 15 MSP 3400C 5. I2C Bus Interface: Device and Subaddresses As a slave receiver, the MSP 3400C can be controlled via I2C bus. Access to internal memory locations is achieved by subaddressing. The demodulator part and the audio processor part (DFP) have two separate subaddressing register banks. In order to allow for more MSP 3400C ICs to be connected to the control bus, an ADR_SEL pin has been implemented. With ADR_SEL pulled to high, the MSP 3400C responds to changed device addresses, thus two identical devices can be selected. Other devices of the same family will have different subaddresses (e.g. 34x0) By means of the RESET bit in the CONTROL register, all devices with the same device address are reset. The IC is selected by asserting a special device address in the address part of an I2C transmission. A device address pair is defined as a write address (80 hex or 84 hex) and a read address (81 hex or 85 hex). Writing is done by sending the device write address first, followed by the subaddress byte, two address bytes, and two data bytes. For reading, the read address has to be transmitted first by sending the device write address (80 hex or 84 hex), followed by the subaddress byte, and two address bytes. Without sending a stop condition, reading of the addressed data is done by sending the device read address (81 hex or 85 hex) and reading two bytes Table 5-1: I2C Bus Device Addresses ADR_SEL Mode MSP device address Write 80 hex Low Read 81 hex Write 84 hex High Read 85 hex PRELIMINARY DATA SHEET of data. Refer to Fig. 5-1 I2C Bus Protocol and section 5.2. Proposal for MSP 3400C I2C Telegrams. Due to the internal architecture of the MSP 3400C, the IC cannot react immediately to an I2C request. The typical response time is about 0.3 ms. If the addressed processor is not ready for further transmissions on the I2C bus, the clock line I2C_CL is pulled low. This puts the current transmission into a wait state. After a certain period of time, the MSP 3400C releases the clock, and the interrupted transmission is carried on. The I2C Bus lines can be set tristate by switching the IC into "Standby"-mode. I2C-Bus error conditions: In case of any internal error, the MSP's wait-period is extended to 1.77 ms. Afterwards, the MSP does not acknowledge (NAK) the device address. The data line will be left HIGH by the MSP, and the clock line will be released. The master can then generate a STOP condition to abort the transfer. By means of NAK, the master is able to recognize the error state and to reset the IC via I2C-Bus. While transmitting the reset protocol (section. 5.2.4.) to `CONTROL', the master must ignore the not acknowledge bits (NAK) of the MSP. A detailed timing diagram is shown in Fig. 5-1 and Fig. 5-2. Left Open Write 88 hex Read 89 hex Table 5-2: I2C Bus Device and Subaddresses Name CONTROL TEST1 TEST2 WR_DEM RD_DEM WR_DFP RD_DFP AGC PLL_CAP Binary Value 0000 0000 0000 0001 0000 0010 0001 0000 0001 0001 0001 0010 0001 0011 0001 1110 0001 1111 Hex Value 00 01 02 10 11 12 13 1E 1F Function software reset only for internal use only for internal use write address demodulator read address demodulator write address DFP read address DFP read AGC RMS read / write PLL_Cap 16 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C Table 5-3: Control Register Name CONTROL 15 RESET 14..0 0 5.1. Protocol Description Write to DFP or Demodulator Part (long protocol) S daw Wait ACK sub-addr ACK addr-byte high ACK addr-byte low ACK data-byte high ACK data-byte low ACK P Read from DFP Part (long protocol) S daw Wait ACK sub-addr ACK addr-byte high ACK addr-byte low ACK S dar Wait ACK data-byte high Write to Control / Test / AGC / PLL_Cap Registers (short protocol) S daw Wait ACK sub-addr ACK data-byte high ACK data-byte low Read from Control / Test / AGC / PLL_Cap Registers (short protocol) S daw Wait ACK sub-addr ACK S dar Wait ACK data-byte high Note: S = P= daw = dar = ACK = I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Device Address Write Device Address Read Acknowledge-Bit: LOW on I2C_DA from slave (= MSPC, grey) or master (= CCU, hatched) NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (= CCU, hatched) to indicate `End of Read' or from MSPC indicating internal error state (not illustrated) Wait = I2C-Clock line held low by the slave (= MSPC) while interrupt is serviced (<1.77 ms) I2C_DA S I2C_CL Fig. 5-1: I2C bus protocol MICRONAS INTERMETALL 1 0 P (MSB first; data must be stable while clock is high) CCC CCC CCC CCC ACK CC CCC CC CCC CC CCC ACK data-byte low NAK ACK data-byte low NAK P P P 17 MSP 3400C (Data: LSB first) TI2C4 PRELIMINARY DATA SHEET FIM TI2C3 I2C_CL TI2C1 I2C_DA as input TI2C5 TI2C6 TI2C2 TIMOL2 I2C_DA as output TIMOL1 Fig. 5-2: I2C bus timing diagram 5.2. Proposal for MSP 3400C I2C Telegrams 5.2.1. Symbols daw dar < > aa dd device address write device address read Start Condition Stop Condition Address Byte Data Byte 5.2.2. Write Telegrams 18 PRELIMINARY DATA SHEET MSP 3400C 5.3. Start Up Sequence After power on or RESET, the IC is in an inactive state. The CCU has to transmit the required coefficient set for a given operation via the I2C bus. Initialization must start with the demodulator part. If required for any reason, the audio processing part can be loaded before the demodulator part. The reset pin should not be > 0.45 DVSUP (see recommended operation conditions) before the 5 Volt digital power supply (DVSUP) and the analog power supply (AVSUP) are > 4.75 Volt and the MSP-Clock is running (Delay: 2 ms max, 0.5 ms typ.). This means, if the reset low-high edge starts with a delay of 2 ms after DVSUP> 4.75 Volt and AVSUP>4.75 Volt, even under worst case conditions, the reset is ok. DVSUP/V AVSUP/V 4.75 Oscillator time / ms max. 2 RESETQ 0.45 * DVSUP time / ms min. 2 time / ms Fig. 5-3: Power-up sequence MICRONAS INTERMETALL Note: The reset should not reach high level before the oscillator has started. This requires a reset delay of >2 ms 19 MSP 3400C 6. Programming the Demodulator Part 6.1. Registers: Table and Addresses In Table 6-1, all Write Registers are listed. All transmissions on the control bus are 16 bits wide. Data for the demodulator part has 8 or 12 significant bits. These data have to be inserted LSB bound and filled with zero bits into the 16 bit transmission word. If channel 1 or channel 2 is selected in the channel matrix while any of the parameters are changed, the corresponding output must be muted. Click and crack noise may occur during coefficient changes. Table 4-1 explains how to assign FM carriers to the MSPC-Sound IF channels and the corresponding matrix modes in the audio processing part. PRELIMINARY DATA SHEET Table 6-1: MSP 3400C demodulator write registers Register Protocol Write Address (hex) 00BB 0083 0001 0005 0093 009B 00A3 00AB 1F Function AD_CV MODE_REG FIR_REG_1 FIR_REG_2 DCO1_LO DCO1_HI DCO2_LO DCO2_HI PLL_CAP1) long long long long long long long long short input selection, configuration of AGC and Mute Function, and selection of A/D-converter mode register serial shift register for 6 8 bit, filter coefficient channel 1 (48 bit) serial shift register for 6 8 bit, + 2 12 bit off set (total 72 bit) increment channel 1 Low Part increment channel 1 High Part increment channel 2 Low Part increment channel 2 High Part switchable PLL capacities Table 6-2: MSP 3400C demodulator read registers Register Protocol Read Address (hex) 1F 1E 0023 Function PLL_CAP1) AGC_RMS1) C_AD_BITS short short long switchable PLL capacities RMS value, comparable with reference value A read from this address always responds with 0. This ensures software compatibility with the MSP 3410 readout. Reading 0 from this register signals "No NICAM". 1) The registers PLL_CAP and AGC_RMS are only available in MSP 3400C. In MSP 3410 and MSP 34x0D, this register cannot be accessed. 20 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 6.2. Registers: Functions and Values In the following, the functions of several registers are explained and their (default) values are defined. 6.2.1. Setting of Parameter AD_CV Table 6-3: AD_CV Register AD_CV Bit Range AD_CV [0] AD_CV [6:1] Meaning not used Reference level in case of Automatic Gain Control = on. Constant gain factor when Automatic Gain Control = off . Determination of Automatic Gain or Constant Gain Selection of analog input MSPC-Carrier-Mute Function Programmable Carrier-Mute Level not used Settings must be set to 0 see Table 6-5 see Table 6-6 0 = constant gain 1 = automatic gain 0 = ANALOG IN1 1 = ANALOG IN2 0 = off: no mute 1 = on: mute (see section 4.1.8.) see Table 6-4 must be set to 0 AD_CV [7] AD_CV [8] AD_CV [9] AD_CV [11-10] AD_CV [15-12] Table 6-4: Carrier Mute Level Step 0 1 2 3 AD_CV [11:10] binary 00 01 10 11 AD_CV [11:10] decimal 0 1 2 3 Internal reference level for mute active (dBr: relative to MSP 3410 ) 0 dBr -3 dBr -6 dBr -12 dBr Table 6-5: Reference values AD_CV [6:1] for active AGC (AD_CV[7] = 1) Application Input Signal Contains Ref. Value binary 101000 100011 010100 Ref. Value decimal 40 35 20 Range of Input Signal at pin ANA_IN_1+ and ANA_IN_2+ 0.14 - 3 Vpp1) 0.14 - 3 Vpp1) 0.14 - 3 Vpp1) Terrestrial TV SAT ADR 2 FM Carriers 1 or more FM Carriers 1 or more FM Carriers and 1 or more ADR Carriers For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the AD converter may result. Due to the robustness of the internal processing in FM mode, the IC works properly up to and even more than 3 Vpp. In AM mode, of course, no AD converter overflow is allowed. As a consequence, in the AM-mode, the maximum input at pins 41 or 43 must not exceed 1.4 Vpp. MICRONAS INTERMETALL 21 1) MSP 3400C Table 6-6: AD_CV parameters for constant input gain (AD_CV[7]=0) Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1) PRELIMINARY DATA SHEET AD_CV [6:1] Constant Gain 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 Gain 3.00 dB 3.85 dB 4.70 dB 5.55 dB 6.40 dB 7.25 dB 8.10 dB 8.95 dB 9.80 dB 10.65 dB 11.50 dB 12.35 dB 13.20 dB 14.05 dB 14.90 dB 15.75 dB 16.60 dB 17.45 dB 18.30 dB 19.15 dB 20.00 dB Input Level at pin ANA_IN1+ and ANA_IN2+ maximum input level1): 3 Vpp (FM) or 1.4 Vpp (AM) maximum input level: 0.14 Vpp1) For signals above 1.4 Vpp, the minimum gain of 3 dB is switched and overflow of the AD converter may result. Due to the robustness of the internal processing in FM mode, the IC works properly up to and even more than 3 Vpp. In AM mode, of course, no AD converter overflow is allowed. As a consequence, in the AM-mode, the maximum input at pins 41 or 43 must not exceed 1.4 Vpp. 22 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 6.2.2. Control Register `MODE_REG' The register `MODE_REG' contains the control bits determining the operation mode of the MSP 3400C; Table 6-7 explains all bit positions. Table 6-7: Control word `MODE_REG': All bits are "0" after power-on-reset Bit [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Function DMA_SYNC1) DCTR_TRI I2S_TRI I2S Mode1) I2S_WS Mode Audio_CL_OUT not used FM1 FM2 AM HDEV MSPC-channel 1 mode MSPC-channel 1/2 mode High Deviation Mode (channel matrix must be sound A ) 0 : FM 1 : AM 0 : normal mode 1 : high deviation mode must be 1 mode of Pins S_CL and S_ID see table 6-10 see table 6-10 Mode of ADR Interface additional gain in AM-mode 0 : Tristate 1 : Active 0 : Gain = 6 dB 1 : Gain = 0 dB 0 : use FIR_REG_1 1 : use FIR_REG_2 0 : normal mode 1 : ADR mode 0 : 0 dB 1 : +12 dB Comment Synchronization to DMA Digital control out 0/1 tristate I2S outputs tristate (I2S_CL, I2S_WS, I2S_DA_OUT) Master/Slave mode of the I2S bus WS due to the Sony or Philips-Format switch Audio_Clock_Output to tristate Definition 0 : off 1 : on 0 : active 1 : tristate 0 : active 1 : tristate 0 : Master 1 : Slave 0 : Sony 1 : Philips 0 : on 1 : tristate must be 0 Recommendation X 0 0 X X X 0 s.Table 6-8 s.Table 6-8 s.Table 6-8 [10] [11] [12] [13] [14] [15] 1) 2) not used S-Bus Mode2) FM2 FIR Filter Gain (FM2 = Ch1) FM2 FIR Filter Coeff. Set (FM2 = Ch1) ADR AM-Gain 1 0 0 0 X 0 X: Depending on mode In case of synchronization to DMA, no I2S-slave mode possible. In case of I2S-slave mode, no synchronization to DMA allowed. I2S-Slave mode dominates. The normal operation mode is `Tristate'; SBUS is only used in conjunction with DMA. MICRONAS INTERMETALL 23 MSP 3400C Table 6-8: Channel modes `MODE_REG [7-9]` FM1 FM2 bit[7] 0 1 X X AM bit[8] 0 0 1 X HDEV bit[9] 0 0 0 1 channel 1 mute FM2 AM FM-Mono (high deviation) PRELIMINARY DATA SHEET channel 2 FM-Mono (FM1) FM1 AM FM-Mono (high deviation) 6.2.3. FIR-Filter Switches To simplify programming of the MSP 3400C, two additional switches have been implemented. The FIR filter for channel1/FM2 can use either FIR_REG_1 coefficients or FIR_REG_2 coefficients by means of MODE_REG[13]. Herewith, it is no longer necessary to transmit both coefficient sets in FM-terrestrial mode. The loading sequence for FIR_REG_2 is sufficient. The additional gain of +6 dB in channel1/FM2 can be switched to 0 dB by means of MODE_REG[12]. Together with MODE_REG[13] set to 1, in satellite mode, it is no longer necessary to transmit both FIR filter coefficient sets. The loading sequence for FIR_REG_2 is sufficient. 6.2.4. FIR-Parameter The following data values (see Table 6-9) are to be transferred 8 bits at a time embedded LSB-bound in a 16 bit word. These sequences must be obeyed. To change a coefficient set, the complete block FIR_REG_1 or FIR_REG_2 must be transmitted. The new coefficient set will be active without a load_reg routine. Table 6-9: Loading sequence for FIR-coefficients WRITE_ADR = FIR_REG_1(Channel 1: FM2) No. 1 2 3 4 5 6 Symbol Name FM2_Coeff. (5) FM2_Coeff. (4) FM2_Coeff. (3) FM2_Coeff. (2) FM2_Coeff. (1) FM2_Coeff. (0) Bits 8 8 8 8 8 8 Value see Table 6-10. WRITE_ADR = FIR_REG_2 (Channel 2: FM1/FM mono) No. 1 2 3 4 5 6 7 8 9 Symbol Name * IMREG1 (8 LSBS) * IMREG1 / IMREG2 (4 MSBs / 4 LSBs) * IMREG2 (8 MSBs) FM_Coef (5) FM_Coef (4) FM_Coef (3) FM_Coef (2) FM_Coef (1) FM_Coef (0) Bits 8 8 8 8 8 8 8 8 8 Value 04 HEX 40 HEX 00 HEX see Table 6-10. * IMREG_1/2: Two 12-bit off-set constants 24 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C Table 6-10: 8-bit FIR-coefficients (decimal integer) for MSP 3410D; reset status: all coefficients are "0" Coefficients for FIR1 0001hex and FIR2 0005hex Terrestrial TV-Standards FM - Satellite FIR filter corresponds to a bandpass with a bandwidth of B = 130 to 500 kHz B fc frequency 500 kHz FIR2 -1 -1 Autosearch FIR2 75 19 36 35 39 40 0 0 B/G-,D/K-,M-Dual FM Coef(i) 0 1 2 3 4 5 MODE-REG[12] MODE-REG[13] FIR2 3 18 27 48 66 72 0 1 130 kHz FIR2 73 53 64 119 101 127 1 1 180 kHz FIR2 9 18 28 47 55 64 1 1 200 kHz FIR2 3 18 27 48 66 72 1 1 280 kHz FIR2 -8 -8 4 6 78 107 1 1 380 kHz FIR2 -1 -9 -16 5 65 123 1 1 -8 2 59 126 1 1 MODE_REG[12] should be set to 0 (= 6 dB gain) if the level of the FM2-carrier processed in MSP-Ch1 is appr. 7 dB below the FM1-carrier of MSP-Ch2. If both carriers have the same level, MODE_REG[12] must be set to 1 (=0 dB gain). MODE_REG[13]: If in MSP-Channel 1 and 2 the same bandwidth is required, it is sufficient to transmit FIR_REG2 only and to set MODE_REG[13] to 1. For compatibility (besides the above programming), the FIR-filter programming as used for the MSP 3410B is also possible. ADR coefficients are listed in the DRP-data sheet. The 130 kHz coefficients are based on subcarriers, which are 7 dB below an existent main carrier. MICRONAS INTERMETALL 25 MSP 3400C 6.2.5. DCO-Increments For a chosen TV standard, a corresponding set of 24-bit increments determining the mixing frequencies of the quadrature mixers, has to be written into the IC. In Table 6-11, several examples of DCO increments are listed. It is necessary to divide them into low part and high part. The formula for the calculation of the increments for any chosen IF-Frequency is as follows: INCRdez = int(f/fs 224) with: int = integer function f = IF-frequency in MHz fS = sampling frequency (18.432 MHz) Conversion of INCR into hex-format and separation of the 12-bit low and high parts lead to the required increments. (DCO1_HI or _LO for channel 1, DCO2_HI or LO for channel 2). PRELIMINARY DATA SHEET Table 6-11: DCO increments for the MSP 3400C; frequency in MHz, increments in Hex Frq. MHz 4.5 5.04 5.5 5.58 5.7421875 6.0 6.2 6.5 6.552 7.02 7.38 DCO_HI 03E8 0460 04C6 04D8 04FC 0535 0561 05A4 05B0 0618 0668 DCO_LO 0000 0000 038E 0000 00AA 0555 0C71 071C 0000 0000 0000 5.76 5.85 5.94 6.6 6.65 6.8 7.2 7.56 0500 0514 0528 05BA 05C5 05E7 0640 0690 0000 0000 0000 0AAA 0C71 01C7 0000 0000 Frq. MHz DCO_HI DCO_LO 26 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 6.4. Software Proposals for Multistandard TV-Sets To familiarize the reader with the programming scheme of the MSP 3400C, two examples in the shape of flow diagrams are shown in the following sections. 6.4.1. Multistandard System B/G German DUAL FM Fig. 6-1 shows a flow diagram for the CCU software, applied for the MSP 3400C in a TV set, which facilitates all standards according to System B/G. For the instructions used in the diagram, please refer to Table 6-12. After having switched on the TV-set and having initialized the MSP 3400C (LOAD_SEQ_1/2), FM-mono sound is available. Fig. 6-1 shows how to check for any stereo or bilingual audio information in channel 1. If successful, the MSP 3400C must be switched to the desired audio mode. 6.3. Sequences to Transmit Parameters and to Start Processing After having been switched on, the MSPC must be initialized by transmitting the parameters according to the LOAD_SEQ_1/2 of Table 6-12. In the MSPC, the initialization sequence must no longer be terminated by transmitting LOAD_REG_1/2. The transmitted data are active as soon as the corresponding I2C telegram has finished. Therefore, while changing parameters of the demodulator section, a mute is recommended for the affected channel (LOAD_SEQ_1/2: mute all FM, LOAD_SEQ_1: switch audio processing to channel2/FM1 or mute channel1/FM2). Otherwise, distorted sound may occur while switching. For FM-stereo operation, the evaluation of the identification signal must be performed. For positive identification check, the MSP 3400C sound channels have to be switched corresponding to the detected operation mode. Table 6-12: Sequences to initialize and start the MSP 3400C LOAD_SEQ_1/2: General Initialization 1. AD_CV 2. FIR_REG_1 3. FIR_REG_2 4. MODE_REG 5. DCO1_LO 6. DCO1_HI 7. DCO2_LO 8. DCO2_HI FM_IDENT_CHECK: Decoding of the identification signal 1. Evaluation of the stereo detection register (DFP register 0018hex, high part) 2. If necessary, switch the corresponding sound channels within the audio processing part LOAD_SEQ_1: Reinitialization of Channel 1 without affecting Channel 2 1. FIR_REG_1 2. MODE_REG 3. DCO1_LO 4. DCO1_HI (6 8 bit) (12 bit) (12 bit) MICRONAS INTERMETALL 27 MSP 3400C START LOAD_SEQ_1/2 Channel 1: FM2 Parameter Channel 2: FM1 Parameter Audio Processing Init PRELIMINARY DATA SHEET 6.4.3. Automatic Search Function for FM-Carrier Detection The AM demodulation ability of the MSP 3400C offers the possibility to calculate the "field strength" of the momentarily selected FM carrier, which can be read out by the CCU. In SAT receivers, this feature can be used to make automatic FM carrier search possible. Therefore, the MSPC has to be switched to AM-mode (MODE_REG[8]), FM-Prescale must be set to 7Fhex=+127dez, and the FM DC Notch must be switched off. The sound-IF frequency range must now be "scanned" in the MSPC-channel 2 by means of the programmable quadrature mixer with an appropriate incremental frequency (i.e. 10 kHz). < -t FM_ IDENT_CHECK 0x0018 After each incrementation, a field strength value is available at the quasi-peak detector output (quasi-peak detector source must be set to FM), which must be examined for relative maxima by the CCU. This results in either continuing search or switching the MSP 3400C back to FM demodulation mode. During the search process, the FIR_REG_2 must be loaded with the coefficient set "AUTOSEARCH", which enables small bandwidth, resulting in appropriate field strength characteristics. The absolute field strength value (can be read out of "quasi peak detector output FM1") also gives information on whether a main FM carrier or a subcarrier was detected, and as a practical consequence, the FM bandwidth (FIR_REG_1/2) and the deemphasis (50 s or adaptive) can be switched automatically. Due to the fact that a constant demodulation frequency offset of a few kHz, leads to a DC-level in the demodulated signal, a further fine tuning of the found carrier can be achieved by evaluating the "DC Level Readout FM1". Therefore, the FM DC Notch must be switched on, and the demodulator part must be switched back to FM-demodulation mode. For a detailed description of the automatic search function, please refer to the corresponding MSP 3400C Windows software. Note: The automatic search is still possible by evaluating only the DC Level Readout FM1 (DC Notch On) as it is described with the MSP 3410, but the above mentioned method is faster. 6.4.4. Automatic Standard Detection The AM demodulation ability of the MSP 3400 C enables a simple method of deciding between standard B/G (FM-carrier at 5.5 MHz) and standard I (FM-carrier at 6.0 MHz). It is achieved by tuning the MSP 3400C in the AM-mode to the two discrete frequencies and evaluating the field strength via the DC level register or the quasi-peak detector output (Mode_Reg, DC Notch, FM Prescale as described in section 6.4.3.). MICRONAS INTERMETALL Pause Bilingual Set FM Matrix: To NO_MATRIX Set Channel Matrix: To SOUND A or B Mono Set FM Matrix: To NO_MATRIX > -t & < t Set Channel Matrix: To SOUNDA Stereo Set FM Matrix: To G/KMATRIX Set Channel Matrix: To STEREO >t Fig. 6-1: CCU software flow diagram: Standard B/G, t = threshold value for stereo/bilingual detection START LOAD_SEQ_1/2 MSP-Channel 1: FM2-Parameter MSP-Channel 2: FM1-Parameter Audio Processing Init STOP Fig. 6-2: CCU software flow diagram: SAT-mode 6.4.2. Satellite Mode Fig. 6-2 shows the simple flow diagram to be used for the MSP 3400C in a satellite receiver. For FM-mono operation, the corresponding FM carrier should preferably be processed at the MSPC-channel 2 or at the MSPC-channel 1 with FIR gain = 0 dB. 28 PRELIMINARY DATA SHEET MSP 3400C 7. Programming the Audio Processing Part 7.1. Summary of the DSP Control Registers Control registers are 16 bit wide. Transmissions via I2C bus have to take place in 16 bit words. Single data entries are 8 bit. Some of the defined 16 bit words are divided into low and high byte, thus holding two different control entities. All control registers are readable. Note: Unused parts of the 16 bit registers must be zero. Table 7-1: DSP Control Registers Name Volume loudspeaker channel Volume / Mode loudspeaker channel Balance loudspeaker channel [L/R] Balance Mode loudspeaker Bass loudspeaker channel Treble loudspeaker channel Loudness loudspeaker channel Loudness Filter Characteristic Spatial effect strength loudspeaker ch. Spatial effect mode/customize Volume headphone channel Volume / Mode headphone channel Volume SCART channel Volume / Mode SCART channel Loudspeaker channel source Loudspeaker channel matrix Headphone channel source Headphone channel matrix SCART1 channel source SCART1 channel matrix I2S channel source I2S channel matrix Quasi-peak detector source Quasi-peak detector matrix Prescale SCART Prescale FM FM matrix 000chex 000bhex 000ahex 0009hex 0008hex 0007hex 0006hex 0005hex 0002hex 0003hex 0004hex 0001hex I2C Bus Address 0000hex High/ Low H L H L H H H L H L H L H L H L H L H L H L H L Adjustable Range, Operational Modes [+12 dB ... -114 dB, MUTE] 1/8 dB Steps, Reduce Volume / Tone Control [0..100 / 100 % and vv][-127..0 / 0 dB and vv] [Linear mode / logarithmic mode] [+20 dB ... -12 dB] [+15 dB ... -12 dB] [0 dB ... +17 dB] [NORMAL, SUPER_BASS] [-100%...OFF...+100%] [SBE, SBE+PSE] [+12 dB ... -114 dB, MUTE] 1/8 dB Steps, Reduce Volume / Tone Control [00hex ... 7Fhex],[+12 dB ... -114 dB, MUTE] [Linear mode / logarithmic mode] [FM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [FM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [FM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [FM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO...] [FM, NICAM, SCART, I2S1, I2S2] Reset Mode MUTE 00hex 100%/100% linear mode 0 dB 0 dB 0 dB NORMAL OFF SBE+PSE MUTE 00hex 00hex linear mode FM SOUNDA FM SOUNDA FM SOUNDA FM SOUNDA FM EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE E EE E EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE E EE E [SOUNDA, SOUNDB, STEREO, MONO...] [00hex ... 7Fhex] [00hex ... 7Fhex] [NO_MAT, GSTEREO, KSTEREO] SOUNDA 00hex 00hex NO_MAT 000dhex 000ehex H H L MICRONAS INTERMETALL 29 MSP 3400C PRELIMINARY DATA SHEET Name Deemphasis FM Adaptive Deemphasis FM Prescale I2S2 ACB Register (SCART Switches and DIG_OUT Pins) Beeper Identification Mode Prescale I2S1 FM DC Notch Mode Tone Control Equalizer loudspeaker ch. band 1 Equalizer loudspeaker ch. band 2 Equalizer loudspeaker ch. band 3 Equalizer loudspeaker ch. band 4 Equalizer loudspeaker ch. band 5 Automatic Volume Correction Volume Subwoofer channel Subwoofer Channel Corner Frequency Subwoofer: Complementary Highpass Balance headphone channel [L/R] Balance Mode headphone Bass headphone channel Treble headphone channel Loudness headphone channel Loudness filter characteristic I2C Bus Address 000fhex High/ Low H L Adjustable Range, Operational Modes [OFF, 50 s, 75 s, J17] [OFF, WP1] [00hex ... 7Fhex] Bits [15..0] [00hex ... 7Fhex]/[00hex ... 7Fhex] [B/G, M] [00hex ... 7Fhex] [ON, OFF] [BASS/TREBLE, EQUALIZER] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [+12 dB ... -12 dB] [off, on, decay time] [0dB ... -30 dB, mute] [50 Hz ... 400 Hz] [off, on] [0...100 / 100% and vv][-127...0 / 0 dB and vv] [Linear mode / logarithmic mode] [+20 dB ... -12 dB] [+15 dB ... -12 dB] [0 dB ... +17 dB] [NORMAL, SUPER_BASS] Reset Mode 50 s OFF 10hex 00hex 0/0 B/G 10hex ON BASS/TREB 0 dB 0 dB 0 dB 0 dB 0 dB off 0 dB 0012hex 0013hex 0014hex 0015hex 0016hex 0017hex 0020hex 0021hex 0022hex 0023hex 0024hex 0025hex 0029hex 002Chex 002Dhex H H/L H/L L H L H H H H H H H H H L off 100%/100% 0030hex H L linear mode 0 dB 0 dB 0 dB NORMAL 0031hex 0032hex 0033hex H H H L Note: For compatibility to new technical codes of the MSP 3400C, please consider the following compatibility restrictions: If adaptive deemphasis is switched on, 75 s deemphasis must be activated. 30 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 7.1.1. Volume Loudspeaker Channel and Headphone Channel Volume loudspeaker Volume headphone +12 dB +11.875 dB +0.125 dB 0 dB -0.125 dB -113.875dB -114 dB Mute Fast Mute 0000hex 0006hex 11 MSBs 11 MSBs 7F0hex 7EEhex 732hex 730hex 72Ehex Clipping Mode loudspeaker Clipping Mode headphone Reduce Volume Reduce Tone Control Compromise Mode 0000hex 0006hex x000 RESET x001 x010 3 LSBs 3 LSBs 0hex 1hex 2hex 0111 1111 000x 0111 1110 111x 0111 0011 001x 0111 0011 000x 0111 0010 111x 0000 0001 001x 012hex 0000 0001 000x 010hex 0000 0000 xxxx 00xhex RESET 1111 1111 111x FFEhex If the clipping mode is set to "Reduce Volume", the following clipping procedure is used: To prevent severe clipping effects with bass, treble, or equalizer boosts, the internal volume is automatically limited to a level where, in combination with either bass, treble, or equalizer setting, the amplification does not exceed 12 dB. If the clipping mode is "Reduce Tone Control", the bass or treble value is reduced if amplification exceeds 12 dB. If the equalizer is switched on, the gain of those bands is reduced, where amplification together with volume exceeds 12 dB. If the clipping mode is "Compromise Mode", the bass or treble value and volume are reduced half and half if amplification exceeds 12 dB (see example below). If the equalizer is switched on, the gain of those bands is reduced half and half, where amplification together with volume exceeds 12 dB. The highest given positive 11-bit number (7F0hex) yields in a maximum possible gain of 12 dB. Decreasing the volume register by 1 LSB decreases the volume by 0.125 dB. Volume settings lower than the given minimum mute the output. With large scale input signals, positive volume settings may lead to signal clipping. With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any audible DC plops. Going back from Fast Mute should be done to the volume step before Fast Mute was activated. Example: Red. Volume Red. Tone Con. Compromise Vol.: +6 dB 3 6 4.5 Bass: +9 dB 9 6 7.5 Treble: +5 dB 5 5 5 MICRONAS INTERMETALL 31 MSP 3400C 7.1.2. Balance Channel Loudspeaker and Headphone PRELIMINARY DATA SHEET Logarithmic Mode Balance loudspeaker channel [L/R] Balance headphone channel [L/R] Left -127 dB, Right 0 dB Left -126 dB, Right 0 dB Left -1 dB, Right 0 dB Left 0 dB, Right 0 dB 0001hex 0030hex 0111 1111 0111 1110 0000 0001 0000 0000 RESET 1111 1111 1000 0001 1000 0000 H H 7Fhex 7Ehex 01hex 00hex FFhex 81hex 80hex Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. In linear mode, a step by 1 LSB decreases or increases the balance by about 0.8% (exact figure: 100/127). In logarithmic mode, a step by 1 LSB decreases or increases the balance by 1 dB. Balance Mode loudspeaker Balance Mode headphone linear logarithmic 0001hex 0030hex xxx0 RESET xxx1 LSB LSB Left 0 dB, Right -1 dB 0hex 1hex Left 0 dB, Right -127 dB Left 0 dB, Right -128 dB Linear Mode Balance loudspeaker channel [L/R] Balance headphone channel [L/R] Left muted, Right 100% Left 0.8%, Right 100% Left 99.2%, Right 100% Left 100%, Right 100% Left 100%, Right 99.2% Left 100%, Right 0.8% Left 100%, Right muted 0001hex 0030hex 0111 1111 0111 1110 0000 0001 0000 0000 RESET 1111 1111 1000 0010 1000 0001 H H 7Fhex 7Ehex 01hex 00hex FFhex 82hex 81hex 32 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 7.1.4. Treble Loudspeaker and Headphone Channel Treble loudspeaker Treble headphone +15 dB +14 dB +1 dB +1/8 dB 0 dB -1/8 dB -1 dB -11 dB -12 dB FFhex F8hex A8hex A0hex With positive treble settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set treble to a value that, in conjunction with volume, would result in an overall positive gain. Loudspeaker channel: Treble and Equalizer cannot work simultaneously (see Table: Mode Tone Control). If Equalizer is used, Bass and Treble coefficients must be set to zero and vice versa. 0003hex 0032hex 0111 1000 0111 0000 0000 1000 0000 0001 0000 0000 RESET 1111 1111 1111 1000 1010 1000 1010 0000 H H 78hex 70hex 08hex 01hex 00hex FFhex F8hex A8hex A0hex 7.1.3. Bass Loudspeaker and Headphone Channel Bass loudspeaker Bass headphone +20 dB +18 dB +16 dB +14 dB +12 dB +11 dB +1 dB +1/8 dB 0 dB -1/8 dB -1 dB -11 dB -12 dB 0002hex 0031hex 0111 1111 0111 1000 0111 0000 0110 1000 0110 0000 0101 1000 0000 1000 0000 0001 0000 0000 RESET 1111 1111 1111 1000 1010 1000 1010 0000 H H 7Fhex 78hex 70hex 68hex 60hex 58hex 08hex 01hex 00hex With positive bass settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set bass to a value that, in conjunction with volume, would result in an overall positive gain. Loudspeaker channel: Bass and Equalizer cannot work simultaneously (see Table: Mode Tone Control). If Equalizer is used, Bass and Treble coefficients must be set to zero and vice versa. MICRONAS INTERMETALL 33 MSP 3400C 7.1.5. Loudness Channel Loudness loudspeaker Loudness headphone +17 dB +16 dB +1 dB 0 dB Loudspeaker and Headphone PRELIMINARY DATA SHEET 7.1.6. Spatial Effects Loudspeaker Channel Spatial effect strength loudspeaker channel Enlargement 100% 0005hex 0111 1111 0011 1111 0000 0001 0000 0000 RESET 1111 1111 1100 0000 1000 0000 0005hex 0000 RESET 0000 0010 H 7Fhex 3Fhex 01hex 00hex FFhex C0hex 80hex [7:4] 0hex 0hex 2hex 0004hex 0033hex 0100 0100 0100 0000 0000 0100 0000 0000 RESET H H Enlargement 50% 44hex 40hex 04hex 00hex Reduction 50% Reduction 100% Enlargement 1.5% Effect off Reduction 1.5% Mode Loudness loudspeaker Mode Loudness headphone Normal (constant volume at 1 kHz) Super Bass (constant volume at 2 kHz) 0004hex 0033hex 0000 0000 RESET 0000 0100 L L 00hex 04hex Spatial Effect Mode Stereo Basewidth Enlargement (SBE) and Pseudo Stereo Effect (PSE). (Mode A) Stereo Basewidth Enlargement (SBE) only. (Mode B) Spatial Effect Customize Coefficient max high pass gain 2/3 high pass gain 1/3 high pass gain min high pass gain automatic 0005hex 0000 RESET 0010 0100 0110 1000 [3:0] 0hex 2hex 4hex 6hex 8hex Loudness increases the volume of low and high frequency signals, while keeping the amplitude of the 1 kHz reference frequency constant. The intended loudness has to be set according to the actual volume setting. Because loudness introduces gain, it is not recommended to set loudness to a value that ,in conjunction with volume, would result in an overall positive gain. By means of `Mode Loudness', the corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz. There are several spatial effect modes available: Mode A (low byte = 00hex) is compatible to the formerly used spatial effect. Here, the kind of spatial effect depends on the source mode. If the incoming signal is in mono mode, Pseudo Stereo Effect is active; for stereo signals, Pseudo Stereo Effect and Stereo Basewidth Enlargement is effective. The strength of the effect is controllable by the upper byte. A negative value reduces the stereo image. A rather strong spatial effect is recommended for small TV sets where loudspeaker spacing is rather close. For large screen TV sets, a more moderate spatial effect is recommended. In mode A, even in case of stereo input signals, Pseudo Stereo Effect is active, which reduces the center image. In Mode B, only Stereo Basewidth Enlargement is effective. For mono input signals, the Pseudo Stereo Effect has to be switched on. 34 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 7.1.8. Channel Source Modes Loudspeaker channel source Headphone channel source SCART channel source I2S channel source 0007hex xxx0 RESET xxx1 LSB 0hex 1hex Quasi-peak detector source FM NONE (MSP3410: NICAM) SCART 0008hex 0009hex 000ahex 000bhex 000chex 0000 0000 RESET 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 H H H H H 00hex 01hex 02hex 03hex 04hex 05hex 06hex It is worth mentioning, that all spatial effects affect amplitude and phase response. With the lower 4 bits, the frequency response can be customized. A value of 0000bin yields a flat response for center signals (L = R) but a high pass function of L or R only signals. A value of 0110bin has a flat response for L or R only signals but a lowpass function for center signals. By using 1000bin, the frequency response is automatically adapted to the sound material by choosing an optimal high pass gain. 7.1.7. Volume SCART Volume Mode SCART linear logarithmic Linear Mode Volume SCART OFF 0 dB gain (digital full scale (FS) to 2 VRMS output) +6 dB gain (-6 dBFS to 2 VRMS output) 0007hex 0000 0000 RESET 0100 0000 H 00hex 40hex SBUS12 SBUS34 I2S1 I2S2 0111 1111 7Fhex Note: For Headphone output it is also possible to select a subwoofer signal derived from the Loudspeaker channel. For more details see section 7.1.23. Logarithmic Mode Volume SCART +12 dB +11.875 dB +0.125 dB 0 dB -0.125 dB -113.875 dB -114 dB Mute 0007hex 11 MSBs 7F0hex 7EEhex 732hex 730hex 72Ehex 0111 1111 000x 0111 1110 111x 0111 0011 001x 0111 0011 000x 0111 0010 111x 0000 0001 001x 012hex 0000 0001 000x 010hex 0000 0000 0000 000hex RESET MICRONAS INTERMETALL 35 MSP 3400C 7.1.9. Channel Matrix Modes (see also Table 4-1) Loudspeaker channel matrix Headphone channel matrix SCART channel matrix I2S channel matrix Quasi-peak detectormatrix SOUNDA / LEFT / MSP-IF-CHANNEL2 SOUNDB / RIGHT / MSP-IF-CHANNEL1 STEREO MONO SUM/DIFF AB_XCHANGE INVERT_B 0008hex 0009hex 000ahex 000bhex 000chex 0000 0000 RESET 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 L L L L L 00hex 10hex 20hex 30hex 40hex 50hex 60hex 7.1.11. FM Prescale Volume Prescale FM (normal FM mode) OFF Maximum Volume (28 kHz deviation 1) recommended FIRbandwidth: 130 kHz) Deviation 50 kHz1) recommended FIRbandwidth: 200 kHz Deviation 75 kHz1) recommended FIRbandwidth: 200 or 280 kHz Deviation 150 kHz1) recommended FIRbandwidth: 380 kHz Maximum deviation 192 kHz1) recommended FIRbandwidth: 380 kHz Prescale for adaptive deemphasis WP1 recommended FIRbandwidth: 130 kHz Volume Prescale FM (High Deviation Mode) Deviation 150 kHz1) recommended FIRbandwidth: 380 kHz Maximum deviation 384 kHz1) recommended FIRbandwidth: 500 kHz PRELIMINARY DATA SHEET 000ehex 0000 0000 RESET 0111 1111 H 00hex 7Fhex 0100 1000 48hex 0011 0000 30hex 0001 1000 18hex 0001 0011 13hex 0001 0000 10hex The sum/difference mode can be used together with the quasi-peak detector to determine the sound material mode. If the difference signal on channel B (right) is near to zero, and the sum signal on channel A (left) is high, the incoming audio signal is mono. If there is a significant level on the difference signal, the incoming audio is stereo. 7.1.10. SCART Prescale Volume Prescale SCART OFF 0 dB gain (2 VRMS input to digital full scale) +14 dB gain (400 mVRMS input to digital full scale) 000dhex 0000 0000 RESET 0001 1001 0111 1111 H 00hex 19hex 7Fhex 000ehex H 0011 0000 30hex 0001 0011 13hex For the High Deviation Mode, the FM prescaling values can be used in the range between 13hex to 30hex. Please consider the internal reduction of 6 dB for this mode. The FIR-bandwidth should be selected to 500 kHz. 1) Given deviations will result in internal digital full scale signals. Appropriate clipping headroom has to be set by the customer. This can be done by decreasing the listed values by a specific factor. 36 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 7.1.15. I2S1 and I2S2 Prescale Prescale I2S1 Prescale I2S2 OFF 0016hex 0012hex 00hex 10hex RESET 7Fhex H H 7.1.12. FM Matrix Modes (see also Table 4-1) FM matrix NO MATRIX GSTEREO KSTEREO 000ehex 0000 0000 RESET 0000 0001 0000 0010 L 00hex 01hex 02hex 0 dB gain +18 dB gain NO_MATRIX is used for terrestrial mono or satellite stereo sound. GSTEREO dematrixes (L+R, 2R) to (2L, 2R) and is used for German dual carrier stereo system (Standard B/G). KSTEREO dematrixes (L+R, L-R) to (2L, 2R) and is used for the Korean dual carrier stereo system (Standard M). 7.1.13. FM Fixed Deemphasis Deemphasis FM 50 s 75 s J17 OFF 000fhex 0000 0000 RESET 0000 0001 0000 0100 0011 1111 H 00hex 01hex 04hex 3Fhex 7.1.16. ACB Register, Definition of the SCARTSwitches and DIG_CTR_OUT Pins ACB Register DSP In Selection of Source: SC_1_IN MONO_IN SC_2_IN SC_3_IN SC_1_OUT_L/R Selection of Source: SC_3_IN SC_2_IN MONO_IN DA_SCART SC_2_OUT_L/R Selection of Source: DA_SCART SC_1_IN MONO_IN DIG_CTR_OUT1 low high DIG_CTR_OUT2 low high 0013hex H xxxx xxxx xxxx xxxx xx00 xx01 xx10 xx11 RESET xxxx xxxx xxxx xxxx 00xx 01xx 10xx 11xx RESET 7.1.14. FM Adaptive Deemphasis FM Adaptive Deemphasis WP1 OFF WP1 000fhex 0000 0000 RESET 0011 1111 L 00hex 3Fhex xx00 xxxx xx01 xxxx xx10 xxxx x0xx xxxx x1xx xxxx 0xxx xxxx 1xxx xxxx RESET RESET RESET Must be set to `OFF' in case of dual carrier stereo (German or Korean). If `ON', FM fixed deemphasis must be set to 75 s. RESET: The RESET state is taken at the time of the first write transmission on the control bus to the audio processing part (DSP). By writing to the ACB register first, the RESET state can be redefined. MICRONAS INTERMETALL 37 MSP 3400C 7.1.17. Beeper Beeper Volume OFF Maximum Volume (full digital scale FDS) Beeper Frequency 16 Hz (lowest) 1 kHz 4 kHz (highest) 0014hex 0000 0000 RESET 0111 1111 0014hex 0000 0001 0100 0000 1111 1111 H 00hex 7Fhex L 01hex 40hex FFhex 7.1.19. FM DC Notch FM DC Notch ON OFF PRELIMINARY DATA SHEET 0017hex 0000 0000 Reset 0011 1111 L 00hex 3Fhex The DC compensation filter (FM DC Notch) for FM input can be switched off. This is used to speed up the automatic search function (see sector 6.4.3.). In normal FMmode, the FM DC Notch should be switched on. 7.1.20. Mode Tone Control Mode Tone Control Bass and Treble Equalizer 00020hex 0000 0000 RESET 1111 1111 H 00hex FFhex A squarewave beeper can be added to the loudspeaker channel and the headphone channel. The addition point is just before loudness and volume adjustment. 7.1.18. Identification Mode Identification Mode Standard B/G (German Stereo) Standard M (Korean Stereo) Reset of Ident-Filter 0015hex 0000 0000 RESET 0000 0001 0011 1111 L 00hex 01hex 3Fhex By means of `Mode Tone Control', Bass/Treble or Equalizer may be activated. To shorten the response time of the identification algorithm after a program change between two FM-stereo capable programs, the reset of ident-filter can be applied. Sequence: 1. Program change 2. Reset ident-filter 3. Wait at least 1 msec. 4. Set identification mode back to standard B/G or M 5. Wait approx. 1 sec. 6. Read stereo detection register 38 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C Different sound sources (e.g. Terrestrial channels, SAT channels or SCART) fairly often don't have the same volume level. Advertisement during movies as well has mostly a different (higher) volume level, than the movie itself. The Automatic Volume Correction (AVC) solves this problem and equalizes the volume levels. The absolute value of the incoming signal is fed into a filter with 16ms attack time and selectable decay time. The decay time must be adjusted as shown in the table above. This attack/decay filter block works similar to a peak hold function. The volume correction value with it's quasi continuous step width is calculated using the attack/decay filter output. The Automatic Volume Correction works with an internal reference level of -18 dBFS. This means, input signals with a volume level of -18 dBFS will not be affected by the AVC. If the input signals vary in a range of -24 dB to 0 dB the AVC compensates this. Example: A static input signal of 1 kHz on Scart has an output level as shown in the table below. Scart Input 0dbr = 2 Vrms 0 dBr -6 dBr -12 dBr -18 dBr -24 dBr -30 dBr Volume Correction -18 dB -12 dB -6 dB -0 dB + 6 dB + 6 dB Main Output 0dBr = 1.4 Vrms -18 dBr -18 dBr -18 dBr -18 dBr -18 dBr -24 dBr 7.1.21. Equalizer Loudspeaker Channel Band 1 (below 120 Hz) Band 2 (Center: 500 Hz) Band 3 (Center: 1.5 kHz) Band 4 (Center: 5 kHz) Band 5 (above 10kHz) +12 dB +11 dB +1 dB +1/8 dB 0 dB -1/8 dB -1 dB -11dB -12 dB 0021hex 0022hex 0023hex 0024hex 0025hex 0110 0000 0101 1000 0000 1000 0000 0001 0000 0000 RESET 1111 1111 1111 1000 1010 1000 1010 0000 H H H H H 60hex 58hex 08hex 01hex 00hex FFhex F8hex A8hex A0hex With positive equalizer settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recommended to set equalizer bands to a value that, in conjunction with volume, would result in an overall positive gain. Equalizer must not be used simultaneously with Bass and Treble (Mode Tone Control must be set to FF to use the Equalizer). 7.1.22. Automatic Volume Correction (AVC) AVC AVC AVC AVC 8 sec 4 sec 2 sec 20 ms on/off off and Reset of int. variables on Decay Time (long) (middle) (short) (very short) 0029hex 0000 RESET 1000 0029hex 1000 0100 0010 0001 [15:12] 0hex 8hex [11:8] 8hex 4hex 2hex 1hex Loudspeaker Volume = 73h = 0 dBFS Scart Prescale = 20h i.e. 2.0 Vrms = 0dBFS To reset the internal variables, the AVC should be switched off and on during any channel or source change. For standard applications, the recommended decay time is 4sec. Note: AVC should not be used in any Dolby Prologic modes, except PANORAMA, where no other than the loudspeaker output is active. MICRONAS INTERMETALL 39 MSP 3400C 7.1.23. Subwoofer on Headphone Output The subwoofer channel is created by combining the left and right loudspeaker channels ( (L+R)/2 ) directly behind the tone control filter block. A third order lowpass filter with programmable corner frequency and volume adjustment respectively to the loudspeaker channel output is performed to the bass-signal. Additionally, at the loudspeaker channels, a complementary high pass filter can be switched on. The subwoofer channel output can be switched to the headphone D/A converter alternatively with the headphone output. 7.2. Exclusions PRELIMINARY DATA SHEET In general, all functions can be switched independently of the others. One exception exists: 1. If the adaptive deemphasis is activated (Reg. 000fhex L), the FM fixed deemphasis (Reg. 000fhex H) must be set to 75 s. Subwoofer Channel Volume Adjust 0 dB -1 dB -29 dB -30 dB Mute 002Chex 0000 0000 RESET 1111 1111 1110 0011 1110 0010 1000 0000 H 00hex FFhex E3hex E2hex 80hex Subwoofer Channel Corner Frequency 50 Hz .... 400 Hz e.g. 50 Hz = 5 int 400 Hz = 40int Headphone Output Headphone Subwoofer Subwoofer: Complementary Highpass HP off HP on 002Dhex H 0000 0101 0010 1000 002Dhex 0000 1000 002Dhex 0000 0001 05hex 28hex [7:4] 0hex 8hex [3:0] 0hex 1hex Note: If subwoofer is chosen for headphone output, the corner frequency must be set to the desired value, before the loudspeaker volume is set. This is to avoid plop noise. 40 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 7.3. Summary of Readable Registers All readable registers are 16 bit wide. Transmissions via I2C bus have to take place in 16 bit words. Single data entries are 8 bit. Some of the defined 16 bit words are divided into low and high byte, thus holding two different control entities. These registers are not writeable. Name Stereo detection register Quasi peak readout left Quasi peak readout right DC level readout FM1/Ch2-L DC level readout FM2/Ch1-R MSP hardware version code MSP major revision code MSP product code MSP ROM version code 001fhex Address 0018hex 0019hex 001ahex 001bhex 001chex 001ehex High/Low H H&L H&L H&L H&L H L H L Output Range [80hex ... 7Fhex] [00hex ... 7FFFhex] [00hex ... 7FFFhex] [00hex ... 7FFFhex] [00hex ... 7FFFhex] [00hex ... FFhex] [00hex ... FFhex] [00hex ... 0Ahex] [00hex ... FFhex] 8 bit two's complement 16 bit binary 16 bit binary 16 bit binary 16 bit binary 7.3.1. Stereo Detection Register Stereo Detection Register Stereo Mode MONO STEREO BILINGUAL 0018hex H 7.3.2. Quasi Peak Detector Quasi peak readout left Quasi peak readout right Quasi peak readout 0019hex 001ahex H+L H+L Reading (two's complement) near zero positive value (ideal reception: 7Fhex) negative value (ideal reception: 80hex) [0hex ... 7FFFhex] values are 16 bit binary The quasi peak readout register can be used to read out the quasi peak level of any input source, in order to adjust all inputs to the same normalized listening level. The refresh rate is 32 kHz. The feature is based on a filter time constant: attack-time: 1.3 ms decay-time: 37 ms MICRONAS INTERMETALL 41 MSP 3400C 7.3.3. DC Level Register DC level readout FM1 DC level readout FM2 DC Level 001bhex 001chex H+L H+L PRELIMINARY DATA SHEET 7.3.6. MSP Product Code Product MSP 3400C MSP 3400 MSP 3410 001fhex 0000 0000 0000 1010 0000 1010 H 00hex 0Ahex1) 0Ahex [0hex ... 7FFFhex] values are 16 bit binary The DC level register measures the DC component of the incoming FM signals (FM1 and FM2). This can be used for seek functions in satellite receivers and for IF FM frequencies fine tuning. For further processing, the DC content of the demodulated FM signals is suppressed. The time constant , defining the transition time of the DC Level Register, is approximately 28 ms. 7.3.4. MSP Hardware Version Code Hardware Version Hardware Version MSP 3400C - C8 001ehex [00hex ... FFhex] 03hex H 1) Note: The MSP 3400 hardware is identical to the MSP 3410. Therefore, the family code readout will show `MSP 3410' instead of its label `MSP 3400'. 7.3.7. MSP ROM Version Code ROM Version Major software revision MSP 3400C - B5 MSP 3400C - C6 MSP 3400C - C8 001fhex [00hex ... FFhex] 0000 0101 0000 0110 0000 1000 05hex 06hex 08hex L A change in the hardware version code defines hardware optimizations that may have influence on the chip's behavior. The readout of this register is identical to the hardware version code in the chip's imprint. 7.3.5. MSP Major Revision Code Major Revision MSP 3400C 001ehex 03hex L A change in the ROM version code defines internal software optimizations, that may have influence on the chip's behavior, e.g. new features may have been included. While a software change is intended to create no compatibility problems, customers that want to use the new functions can identify new MSP 3400C versions according to this number. The readout of this register is identical to the ROM version code in the chip's imprint. The MSP 3400C is the third generation of ICs in the MSP family. 42 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 8. Specifications 8.1. Outline Dimensions 1+0.2 x 45 9 1 61 0.457 2.4 1.27 0.1 15 9 24.2 0.1 27 26 0.4 0.2 4 0.1 15.6 0.1 14 0.1 0.3 3.2 0.2 0.24 0.27 0.06 0...15 2 0.711 0.1 SPGS7004-3/4E SPGS0015-1/2E 10 2 9 25 +0.25 60 0.9 2.4 16 x 1.27 0.1 = 20.32 0.1 1.27 0.1 1.2 x 45 26 27 25 +0.25 43 44 1.9 1.5 4.05 4.75 0.15 Fig. 8-1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensions in mm SPGS0016-4/2E 64 2.5 33 0.2 52 1 32 3.8 0.1 3 1 57.7 0.1 (1) 19.3 0.1 18 0.1 0.3 47 0.1 3.2 0.4 4.8 0.4 1.9 0.27 0.06 1.778 0.05 0.457 0.3 1 0.1 31 x 1.778 = 55.118 0.1 20.1 0.6 1 0.1 0.457 1.778 0.05 25 x 1.778 = 44.47 0.1 1.29 Fig. 8-2: 64-Pin Plastic Shrink Dual Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm Fig. 8-3: 52-Pin Plastic Shrink Dual In Line Package (PSDIP52) Weight approximately 5.5 g Dimensions in mm MICRONAS INTERMETALL 16 x 1.27 0.1 = 20.32 0.1 23.4 24.2 0.1 43 MSP 3400C PRELIMINARY DATA SHEET 23 x 0.8 = 18.4 0.17 0.03 64 65 1.8 17.2 10.3 9.8 16 8 14 41 40 1.8 15 x 0.8 = 12.0 8 0.8 0.8 5 25 1.28 2.70 3 0.2 0.1 20 80 1 24 23.2 Fig. 8-4: 80-Pin Plastic Quad Flat Pack Package (PQFP80) Weight approximately 1.61 g Dimensions in mm SPGS0025-1/1E 8.2. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram AHVSS = connect to AHVSS DVSS = if not used, connect to DVSS - = pin does not exist in this package Pin No. PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin Pin Name 3410D in ( ) Type Connection (if not used) Short Description 1 2 3 4 5 6 7 8 9 10 11 12 1) 2) 16 - 15 14 13 12 11 10 9 8 7 6 14 - 13 12 11 10 9 8 7 - 6 5 9 - 8 7 6 5 4 3 2 1 80 79 S_ID (ADR_WS) NC S_DA_IN (ADR_DA) I2S_DA_IN1 I2S_DA_OUT I2S_WS I2S_CL I2C_DA I2C_CL NC STANDBYQ ADR_SEL OUT LV LV SBUS Ident or ADR wordstrobe1) Not connected SBUS Data input or ADR data output1) I2S1 data input I2S data output I2S wordstrobe I2S clock I2C data I2C clock Not connected Standby (low-active) I2C Bus address select OUT IN OUT IN/OUT IN/OUT IN/OUT IN/OUT LV LV LV LV LV X X LV IN IN X X Depending on MODE_REG[14], the SBUS Interface can be switched into ADR_MODE with S_CL becoming ADR_CL, S_ID becoming ADR_WS and S_DA_IN becoming ADR_DA (see also section 4.5.). Due to compatibility with MSP 3410, it is possible to connect with DVSS as well. 44 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C Pin No. PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin Pin Name 3410D in ( ) Type Connection (if not used) Short Description 13 14 15 16 17 18 19 20 21 22 23 5 4 3 2 - 1 64 63 62 61 60 4 3 - - - 2 1 52 51 50 49 78 77 76 - 75 74 73 72 71 70 69 D_CTR_OUT0 D_CTR_OUT1 NC NC NC AUD_CL_OUT DMA_SYNC XTAL_OUT XTAL_IN TESTEN ANA_IN2+ OUT OUT LV LV LV LV LV Digital control output 0 Digital control output 1 Not connected Not connected Not connected Audio clock output DMA-Sync. Input Crystal oscillator Crystal oscillator Test pin IF input 2 (if ANA_IN1+ is used only, connect to AVSS with 50 pF capacitor) IF common IF input 1 Analog power supply +5 V Analog power supply +5 V Not connected Not connected Analog ground Analog ground Mono input Not connected Reference voltage IF A/D converter Scart input 1 in, right Scart input 1 in, left Analog Shield Ground 1 Scart input 2 in, right Scart input 2 in, left OUT IN OUT IN IN IN LV LV X X X LV 24 25 26 - - - 27 - 28 - 29 30 31 32 33 34 1) 2) 59 58 57 - - - 56 - 55 - 54 53 52 51 50 49 48 47 46 - - - 45 - 44 - 43 42 41 - 40 39 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 ANA_IN- ANA_IN1+ AVSUP AVSUP NC NC AVSS AVSS MONO_IN NC VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L IN IN LV LV X X LV LV X X IN LV LV X IN IN LV LV AHVSS IN IN LV LV Depending on MODE_REG[14], the SBUS Interface can be switched into ADR_MODE with S_CL becoming ADR_CL, S_ID becoming ADR_WS and S_DA_IN becoming ADR_DA (see also section 4.5.). Due to compatibility with MSP 3410, it is possible to connect with DVSS as well. MICRONAS INTERMETALL 45 MSP 3400C PRELIMINARY DATA SHEET Pin No. PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin Pin Name 3410D in ( ) Type Connection (if not used) Short Description 35 36 37 38 39 40 41 42 43 - - - 44 45 46 47 48 49 50 51 52 53 54 55 56 1) 2) 48 47 46 45 44 43 - 42 41 - - - 40 39 38 37 36 35 34 33 - 32 31 30 29 - 38 37 - - - - 36 35 - - - 34 33 32 31 30 29 28 27 - - 26 - 25 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 ASG2 SC3_IN_R SC3_IN_L NC (ASG4) NC (SC4_IN_R) NC (SC4_IN_L) NC AGNDC AHVSS AHVSS NC NC CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R ASG3 NC NC (DACM_SUB) NC DACM_L OUT OUT OUT OUT OUT IN IN AHVSS LV LV LV LV LV LV or AHVSS X X X LV LV X X X LV LV X LV LV AHVSS2) LV LV LV LV Analog Shield Ground 2 Scart input 3 in, right Scart input 3 in, left Not connected Not connected Not connected Not connected Analog reference voltage high voltage part Analog ground Analog ground Not connected Not connected Volume capacitor MAIN Analog power supply 8.0 V Volume capacitor AUX Scart output 1, left Scart output 1, right Reference ground 1 high voltage part Scart output 2, left Scart output 2, right Analog Shield Ground 3 Not connected Not connected Not connected Analog output MAIN, left Depending on MODE_REG[14], the SBUS Interface can be switched into ADR_MODE with S_CL becoming ADR_CL, S_ID becoming ADR_WS and S_DA_IN becoming ADR_DA (see also section 4.5.). Due to compatibility with MSP 3410, it is possible to connect with DVSS as well. 46 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C Pin No. PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin Pin Name 3410D in ( ) Type Connection (if not used) Short Description 57 58 59 60 - - 61 62 63 64 65 66 - - 67 - - 68 1) 2) 28 27 26 25 - - 24 23 22 21 20 19 - - 18 - - 17 24 23 22 21 - - 20 - - 19 18 17 - - 16 - - 15 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DACM_R VREF2 DACA_L DACA_R NC NC RESETQ NC NC NC I2S_DA_IN2 DVSS DVSS DVSS DVSUP DVSUP DVSUP S_CL (ADR_CL) OUT LV X Analog output MAIN, right Reference ground 2 high voltage part Analog output AUX, left Analog output AUX, right Not connected Not connected Power-on-reset Not connected Not connected Not connected I2S2-data input Digital ground Digital ground Digital ground Digital power supply +5 V Digital power supply +5 V Digital power supply +5 V SBUS clock or ADR clock1) OUT OUT LV LV LV LV IN X LV LV LV IN LV X X X X X X OUT LV Depending on MODE_REG[14], the SBUS Interface can be switched into ADR_MODE with S_CL becoming ADR_CL, S_ID becoming ADR_WS and S_DA_IN becoming ADR_DA (see also section 4.5.). Due to compatibility with MSP 3410, it is possible to connect with DVSS as well. MICRONAS INTERMETALL 47 MSP 3400C 8.3. Pin Configurations S_ID NC S_DA_IN I2S_DA_IN1 I2S_DA_OUT I2S_WS I2S_CL I2C_DA I2C_CL S_CL DVSUP DVSS I2S_DA_IN2 NC NC NC RESETQ PRELIMINARY DATA SHEET NC STANDBYQ ADR_SEL D_CTR_OUT0 D_CTR_OUT1 NC NC NC AUD_CL_OUT DMA_SYNC XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN1+ AVSUP 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 DACA_R DACA_L VREF2 DACM_R DACM_L NC NC NC ASG3 SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP CAPL_M MSP 3400C 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L ASG2 NC SC3_IN_L SC3_IN_R NC NC NC AHVSS AGNDC Fig. 8-5: 68-pin PLCC package 48 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C AUD_CL_OUT NC NC D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 S_DA_IN S_ID S_CL DVSUP DVSS I2S_DA_IN2 NC NC NC RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L ASG3 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 64 63 62 61 60 59 58 57 56 55 54 53 52 DMA_SYNC XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN1+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L ASG2 SC3_IN_R SC3_IN_L NC NC NC AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC AUD_CL_OUT D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 S_DA_IN S_ID S_CL DVSUP DVSS I2S_DA_IN2 NC RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L NC 1 2 3 4 5 6 7 8 9 10 52 51 50 49 48 47 46 45 44 43 XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN1+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L SC3_IN_R SC3_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R MSP 3400C 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 MSP 3400C 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Fig. 8-6: 64-pin shrink PSDIP package Fig. 8-7: 52-pin shrink PSDIP package MICRONAS INTERMETALL 49 MSP 3400C ASG2 SC3_IN_R SC3_IN_L NC NC NC NC AGNDC AHVSS AHVSS NC NC PRELIMINARY DATA SHEET SC2_IN_L SC2_IN_R ASG1 SC1_IN_L SC1_IN_R VREFTOP NC MONO_IN AVSS AVSS NC NC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AVSUP AVSUP ANA_IN1+ ANA_IN- ANA_IN2+ TESTEN XTAL_IN XTAL_OUT DMA_SYNC AUD_CL_OUT NC NC D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBY_Q 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R ASG3 NC NC NC DACM_L DACM_R VREF2 DACA_L MSP 3400C 33 32 31 30 29 28 27 26 25 NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 S_DA_IN S_ID S_CL DVSUP DVSUP NC I2S_DA_IN2 DVSS DVSS DVSS DVSUP NC NC NC RESETQ NC DACA_R Fig. 8-8: 80-pin PQFP package 50 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 8.4. Pin Circuits DVSUP P N GND Fig. 8-9: Output Pins 1, 5, 13, 14, and 68 (S_ID, I2S_DA_OUT, D_CTR_OUT0/1, S_CL) DVSUP P DVSUP P N N GND Fig. 8-10: Input Pins 4 and 65 (I2S_DA_IN1/2) GND Fig. 8-15: Input Pin 3 (S_DA_IN) 2.5 V Fig. 8-14: Input Pin 19 (DMA_SYNC) P N GND Fig. 8-11: Input/Output Pins 8 and 9 (I2C_DA, I2C_CL) 3-30 pF 3-30 pF 500 k N 2.5 V Fig. 8-16: Output/Input Pins 18, 20, and 21 (AUD_CL_OUT, XTALIN/OUT) Fig. 8-12: Input Pins 11, 12, 61, and 62 (STANDBYQ, ADR_SEL, RESETQ, TESTEN) ANAIN1+ ANAIN2+ A DVSUP P N GND Fig. 8-13: Input/Output Pins 6 and 7 (I2S_WS, I2S_CL) Fig. 8-17: Input Pins 23-25 and 29 (ANA_IN2+, ANA_IN-, ANA_IN1+, VREFTOP) ANAIN- VREFTOP D MICRONAS INTERMETALL 51 MSP 3400C AHVSUP 3.75 V 0...1.2 mA PRELIMINARY DATA SHEET 16 K Fig. 8-18: Input Pin 28 (MONO_IN) 3.3 K Fig. 8-21: Output Pins 56, 57, 59, and 60 (DACA_L/R, DACM_L/R) 125 K 0...2 V 3.75 V Fig. 8-19: Capacitor Pins 44 and 46 (CAPL_M, CAPL_A) Fig. 8-22: Pin 42 (AGNDC) 40 pF 80 K 300 40 K 3.75 V 3.75 V Fig. 8-20: Input Pins 30, 31, 33, 34, 36, and 37 (SC1-3_IN_L/R) Fig. 8-23: Output Pins 47, 48, 50 and 51 (SC_1/2_OUT_L/R) 52 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 8.5. Electrical Characteristics 8.5.1. Absolute Maximum Ratings Symbol TA TS VSUP1 VSUP2 VSUP3 dVSUP23 PTOT VIdig IIdig VIana IIana IOana IOana ICana 1) 2) 3) 4) Parameter Ambient Operating Temperature Storage Temperature First Supply Voltage Second Supply Voltage Third Supply Voltage Voltage between AVSUP and DVSUP Chip Power Dissipation PLCC68 without Heat Spreader Input Voltage, all Digital Inputs Input Current, all Digital Pins Input Voltage, all Analog Inputs Input Current, all Analog Inputs Output Current, all SCART Outputs Output Current, all Analog Outputs except SCART Outputs Output Current, other pins connected to capacitors Pin Name - - AHVSUP DVSUP AVSUP AVSUP, DVSUP AHVSUP, DVSUP, AVSUP Min. 0 -40 -0.3 -0.3 -0.3 -0.5 Max. 70 125 9.0 6.0 6.0 0.5 Unit C C V V V V 1100 -0.3 VSUP2+0.3 +20 VSUP1+0.3 +5 3), 4) 3) mW V mA1) V mA1) - SCn_IN_s,2) MONO_IN SCn_IN_s,2) MONO_IN SCn_OUT_s2) DACp_s2) CAPL_p,2) AGNDC -20 -0.3 -5 3), 4) 3) 3) 3) positive value means current flowing into the circuit "n" means "1", "2" or "3", "s" means "L" or "R", "p" means "M" or "A" The Analog Outputs are short circuit proof with respect to First Supply Voltage and Ground. Total chip power dissipation must not exceed absolute maximum rating. Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. MICRONAS INTERMETALL 53 MSP 3400C 8.5.2. Recommended Operating Conditions (at TA = 0 to 70 C) Symbol VSUP1 VSUP2 VSUP3 VREIL VREIH tREIL VDMAIL VDMAIH tDMA RDMA VDIGIL VDIGIH tSTBYQ1 Parameter First Supply Voltage Second Supply Voltage Third Supply Voltage RESET Input Low Voltage RESET Input High Voltage RESET Low Time after DVSUP Stable and Oscillator Startup Sync Input Low Voltage Sync Input High Voltage Sync Input Frequency Sync Input Clock High-Level Time Digital Input Low Voltage Digital Input High Voltage STANDBYQ Setup Time before Turn-off of Second Supply Voltage STANDBYQ, ADR_SEL, ADR SEL TESTEN STANDBYQ, DVSUP 500 DMA_SYNC 0.56 Pin Name AHVSUP DVSUP AVSUP RESETQ 0.8 5 Min. 7.6 4.75 4.75 PRELIMINARY DATA SHEET Typ. 8.0 5.0 5.0 Max. 8.4 5.25 5.25 0.45 Unit V V V VSUP2 VSUP2 s 0.44 VSUP1 VSUP1 18.0 kHz ns 0.25 VSUP2 VSUP2 s 0.75 1 I2C-Bus Recommendations VIMIL VIMIH fIM tI2C1 tI2C2 tI2C3 tI2C4 tI2C5 tI2C6 VI2SIL VI2SIH I2C-BUS Input Low Voltage I2C-BUS Input High Voltage I2C-BUS Frequency I2C START Condition Setup Time I2C STOP Condition Setup Time I2C-Clock Low Pulse Time I2C-Clock High Pulse Time I2C-Data Setup Time Before Rising Edge of Clock I2C-Data Hold Time after Falling Edge of Clock I2S-Data Input Low Voltage I2S-Data Input High Voltage I2S_DA_IN1/2 0.75 I2C_CL, I2C_DA I2C_CL, C_DA I2C DA 0.6 I2C_CL I2C_CL, C_DA I2C DA I2C_CL 120 120 500 500 55 55 0.25 1.0 0.3 VSUP2 VSUP2 MHz ns ns ns ns ns ns VSUP2 VSUP2 54 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C Symbol tI2S1 tI2S2 VI2SIDL VI2SIDH fI2SCL RI2SCL fI2SWS Parameter I2S-Data Input Setup Time before Rising Edge of Clock I2S-Data Input Hold Time after Falling Edge of Clock I2S-Input Low Voltage when MSP 3400C in I2S-Slave-Mode I2S-Input High Voltage when MSP 3400C in I2S-Slave-Mode I2S-Clock Input Frequency when MSP 3400C in I2S-Slave-Mode I2S-Clock Input Ratio when MSP 3400C in I2S-Slave-Mode I2S-Wordstrobe Input Frequency when MSP 3400C in I2S-SlaveMode I2S-Wordstrobe Input Setup Time before Rising Edge of Clock when MSP 3400C in I2S-Slave-Mode I2S-Wordstrobe Input Hold Time after Falling Edge of Clock when MSP 3400C in I2S-Slave-Mode SBUS-Data Input Low Voltage SBUS-Data Input Low Current SBUS-Data Input Trigger Voltage SBUS-Data Input Setup Time before Rising Edge of Clock SBUS-Data Input Hold Time after Falling Edge of Clock Pin Name I2S_DA_IN1/2, I2S_CL Min. 20 0 Typ. Max. Unit ns ns I2S_CL, I2S_WS 0.75 I2S_CL 0.9 I2S_WS 32.0 1.024 0.25 VSUP2 VSUP2 MHz 1.1 kHz tI2SWS1 I2S_WS, I2S_CL 60 ns tI2SWS2 0 ns VSBUSIL ISBUSIL VSBUSTRIG tSBUS1 tSBUS2 S_DA_IN 0.9 0.8 S_DA_IN, S_CL 10 0 1.7 0.6 3.2 1.2 V mA V ns ns Crystal Recommendations for Master-Slave Application fP fTOL DTEM RR C0 C1 Parallel Resonance Frequency at 12 pF Load Capacitance Accuracy of Adjustment Frequency Variation versus Temperature Series Resistance Shunt (Parallel) Capacitance Motional (Dynamic) Capacitance 19 -20 -20 8 6.2 24 18.432 +20 +20 25 7.0 MHz ppm ppm pF fF MICRONAS INTERMETALL 55 MSP 3400C PRELIMINARY DATA SHEET Symbol Parameter Pin Name Min. Typ. Max. Unit Load Capacitance Recommendations for Master-Slave Applications CL fCL External Load Capacitance2) Required Open Loop Clock Frequency (Tamb = 25C) XTAL_IN, XTAL_OUT PSDIP PLCC 18.431 1.5 3.3 18.433 pF pF MHz Crystal Recommendations for FM Application (No Master-Slave Mode possible) fP fTOL DTEM RR C0 Parallel Resonance Frequency at 12 pF Load Capacitance Accuracy of Adjustment Frequency Variation versus Temperature Series Resistance Shunt (Parallel) Capacitance -100 -50 8 6.2 18.432 +100 +50 25 7.0 MHz ppm ppm pF Load Capacitance Recommendations for FM Application (No Master-Slave Mode possible) CL External Load Capacitance2) XTAL_IN, XTAL_OUT PSDIP PLCC 1.5 3.3 pF pF Amplitude Recommendation for Operation with External Clock Input (Cload after reset = 22 pF) VXCA External Clock Amplitude XTAL_IN 0.7 Vpp Analog Input and Output Recommendations CAGNDC AGNDC-Filter-Capacitor Ceramic Capacitor in Parallel CinSC VinSC VinMONO RLSC CLSC CVMA CFMA 1) 2) AGNDC -20% -20% 3.3 100 330 +20% 2.0 F nF nF VRMS VRMS k 6.0 nF F +10% nF DC-Decoupling Capacitor in front of SCART Inputs SCART Input Level Input Level, Mono Input SCART Load Resistance SCART Load Capacitance Main/AUX Volume Capacitor Main/AUX Filter Capacitor SCn_IN_s1) -20% MONO_IN SCn_OUT_s1) 10 2.0 CAPL_M, CAPL_A DACM_s, DACA_s1) -10% 10 1 "n" means "1", "2" or "3", "s" means "L" or "R", "p" means "M" or "A" External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop frequency of the internal PLL and to stabilize the frequency in closed-loop operation. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match 18.432 MHz as closely as possible. Due to different layouts of customer PCBs, the matching capacitor size should be defined in the application. The suggested values (1.5 pF/3.3 pF) are figures based on experience with various PCB layouts. 56 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C Symbol Parameter Pin Name Min. Typ. Max. Unit Recommendations for Analog Sound IF Input Signal CVREFTOP VREFTOP-Filter-Capacitor Ceramic Capacitor in Parallel VIF RFM RFM1/FM2 RFC RFV PRIF SUPHF FMMAX Analog Input Range (Complete Sound IF, 0 - 9 MHz) Ratio: FM-Main/FM-Sub Satellite Ratio: FM1/FM2 German FM-System Ratio: Main FM Carrier/Color Carrier Ratio: Main FM Carrier/Luma Components Passband Ripple Suppression of Spectrum Above 9.0 MHz Maximum FM-Deviation (apprx.) normal mode high deviation mode 15 15 - 15 ANA_IN1+, ANA_IN2+, ANA_IN- ANA IN VREFTOP -20% -20% 0.14 10 100 0.8 7 7 - - - - - 2 dB - 3 F nF Vpp dB dB dB dB dB dB 192 360 kHz MICRONAS INTERMETALL 57 MSP 3400C 8.5.3. Characteristics at TA = 0 to 70 C, fCLOCK = 18.432 MHz PRELIMINARY DATA SHEET (Typical values are measured at TA = 25 C, AHVSUP = 8 V, DVSUP = 5 V, AVSUP = 5 V.) Symbol DCO fCLOCK DCLOCK tJITTER VxtalDC tStartup Clock Input Frequency Clock High to Low Ratio Clock Jitter (verification not provided in production test) DC-Voltage Oscillator Oscillator Startup Time at VDD Slew-rate of 1 V / 1 s XTAL_IN, XTAL_OUT 2.5 0.4 2.0 XTAL_IN 45 18.432 55 50 MHz % ps Parameter Pin Name Min. Typ. Max. Unit Test Conditions V ms Power Supply ISUP1A First Supply Current (active) Analog Volume for Main and Aux at 0dB Analog Volume for Main and Aux at -30dB AHVSUP 8.2 5.6 14.8 10.0 22.0 15.0 mA mA at Tj = 27 C ISUP2A ISUP3A ISUP1S f = 18.432 MHz AHVSUP = 8 V DVSUP = 5 V AVSUP = 5 V f = 18.432 MHz DVSUP = 5 V f = 18.432 MHz AVSUP = 5 V STANDBYQ = low VSUP = 8 V Second Supply Current (active) DVSUP 60 65 70 mA Third Supply Current (active) AVSUP 25 mA First Supply Current (standby mode) at Tj = 27 C AHVSUP 2.8 5.0 7.2 mA Audio Clock Output VAPUAC VAPUDC Digital Output VDCTROL VDCTROH I2C Bus VIMOL IIMOH tIMOL1 tIMOL2 I2C-Data Output Low Voltage I2C-Data Output High Current I2C-Data Output Hold Time after Falling Edge of Clock I2C-Data Output Setup Time before Rising Edge of Clock I2C_DA, I2C_CL 15 I2C_DA 0.4 1 V A ns IiMOL = 3 mA VIMOH = 5 V Digital Output Low Voltage Digital Output High Voltage D_CTR_OUT0 D_CTR_OUT1 D CTR OUT1 4.0 0.4 V V IDDCTR = 1 mA IDDCTR = -1 mA Audio Clock Output AC Voltage Audio Clock Output DC Voltage AUD_CL_OUT 1.2 0.4 0.6 Vpp VSUP1 40 pF load 100 ns fIM = 1 MHz DVSUP = 5 V SBus fSB tS1/S2 tS3 fSIO tS6 SBUS-Clock Frequency SBUS-Clock High/Low-Ratio SBUS Setup Time before Ident End Pulse SBUS Ident frequency SBUS-Ident End Pulse Time S_CL, S_ID S_ID 210 S_CL 0.9 210 4608 1.0 1.1 kHz ns ns DVSUP = 5.25 V DVSUP = 5 V 32 kHz ns DVSUP = 5.25 V 58 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C Symbol I2S Bus VI2SOL VI2SOH fI2SCL fI2SWS tI2S1/I2S2 tI2S3 tI2S4 tI2S5 tI2S6 Parameter Pin Name Min. Typ. Max. Unit Test Conditions I2S Output Low Voltage I2S Output High Voltage I2S-Clock Output Frequency I2S-Wordstrobe Output Frequency I2S-Clock High/Low-Ratio I2S-Data Setup Time before Rising Edge of Clock I2S-Data Hold Time after Falling Edge of Clock I2S-Wordstrobe Setup Time before Rising Edge of Clock I2S-Wordstrobe Hold Time after Falling Edge of Clock I2S_WS, I2S_CL, I2S CL I2S_DA_OUT I2S_CL I2S_WS I2S_CL I2S_CL, I2S_DA_OUT 0.4 4.0 1204 32.0 0.9 200 1.0 1.1 V V kHz kHz II2SOL = 1 mA II2SOH = -1 mA DVSUP = 5 V DVSUP = 5 V ns DVSUP = 4.75 V 12 ns DVSUP = 5.25 V I2S_CL, I2S_WS 100 ns DVSUP = 4.75 V 50 ns DVSUP = 5.25 V Analog Ground VAGNDC0 RoutAGN AGNDC Open Circuit Voltage AGNDC Output Resistance at Tj = 27 C from TA = 0 to 70 C AGNDC 3.64 3.73 3.84 V Rload 10 M 3 V VAGNDC 4 V 70 70 125 180 180 k k Analog Input Resistance RinSC SCART Input Resistance at Tj = 27 C from TA = 0 to 70 C MONO Input Resistance at Tj = 27 C from TA = 0 to 70 C SCn_IN_s1) 25 25 MONO_IN 10 10 16 23 23 k k 40 58 58 k k fsignal = 1 kHz, I 0.05 mA RinMONO fsignal = 1 kHz, I 0.1 mA Audio Analog-to-Digital-Converter VAICL Analog Input Clipping Level for Analog-to-Digital-Conversion SCn_IN_s,1) MONO_IN 2.02 2.12 2.22 VRMS fsignal = 1 kHz SCART Outputs RoutSC SCART Output Resistance at Tj = 27 C from TA = 0 to 70 C Deviation of DC-Level at SCART Output from AGNDC Voltage Gain from Analog Input to SCART Output Frequency Response from Analog Input to SCART Output bandwidth: 0 to 20000 Hz Signal Level at SCART-Output during full-scale digital input signal from DSP "s" means "L" or "R", SCn_IN_s1) MONO_IN SCn_OUT_s1) SCn_OUT_s1) 0.20 0.20 -70 0.33 0.46 0.5 +70 k k mV fsignal = 1 kHz, I = 0.1 mA dVOUTSC ASCtoSC frSCtoSC fsignal = 1kHz -1.0 0 +0.5 dB with respect to 1 kHz -0.5 0 +0.5 dB VoutSC SCn_OUT_s1) 1.8 1.9 2.0 VRMS fsignal = 1 kHz 1) "n" means "1", "2" or "3", "p" means "M" or "A" MICRONAS INTERMETALL 59 MSP 3400C PRELIMINARY DATA SHEET Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Main and AUX Outputs RoutMA Main/AUX Output Resistance at Tj = 27 C from TA = 0 to 70 C DC-Level at Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at -30 dB Signal Level at Main/AUX-Output during full-scale digital input signal from DSP for Analog Volume at 0 dB DACp_s1) 2.1 2.1 3.3 4.6 5.0 k k fsignal = 1 kHz, I = 0.1 mA VoutDCMA 1.74 - 1.94 61 2.14 - V mV VoutMA 1.23 1.37 1.51 VRMS fsignal = 1 kHz Analog Performance SNR Signal-to-Noise Ratio from Analog Input to DSP MONO_IN, SCn_IN_s1) 85 88 dB Input Level = -20 dB with resp. to VAICL, fsig = 1 kHz, equally weighted 20 Hz ... 16 kHz2) Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz ... 20 kHz Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz ... 15 kHz3) Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz ... 15 kHz3) from Analog Input to SCART Output MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1) 93 96 dB from DSP to SCART Output 85 88 dB from DSP to Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at -30 dB DACp_s1) 85 78 88 83 dB dB THD Total Harmonic Distortion from Analog Input to DSP MONO_IN, SCn_IN_s1) 0.05 % Input Level = -3 dBr with resp. to VAICL, fsig =1kHz, equally weighted 20 Hz ...16 kHz, RLoad = 30 k2) Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz ... 20 kHz, RLoad = 30 k Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz ... 16 kHz, RLoad = 30 k3) Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz ... 16 kHz, RLoad = 30 k3) from Analog Input to SCART Output MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1) 0.01 0.03 % from DSP to SCART Output 0.01 0.03 % from DSP to Main or AUX Output DACA_s, DACM_s1) 0.01 0.03 % 1) 2) 3) "n" means "1", "2" or "3", "s" means "L" or "R", DSP measured at I2S-Output DSP Input at I2S-Input "p" means "M" or "A" 60 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C Symbol XTALK Parameter Crosstalk attenuation - PLCC68 - PSDIP64 Pin Name Min. Typ. Max. Unit Test Conditions Input Level = -3 dB, fsig = 1 kHz, unused analog inputs connected to ground by Z<1 k equally weighted 20 Hz ... 20 kHz between left and right channel within SCART Input/Output pair (LR, RL) SCn_IN SCn_OUT1) SCn_IN DSP1) DSP SCn_OUT1) PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 80 80 80 80 80 80 dB dB dB dB dB dB 2) 3) between left and right channel within Main or AUX Output pair DSP DACp1) between SCART Input/Output pairs1) D = disturbing program O = observed program D: MONO/SCn_IN SCn_OUT O: MONO/SCn_IN SCn_OUT1) D: MONO/SCn_IN SCn_OUT O: or unsel. MONO/SCn_IN DSP1) D: MONO/SCn_IN SC1_OUT O: DSP SCn_OUT1) D: MONO/SCn_IN unselected O: DSP SC1_OUT1) PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 100 100 95 95 100 100 100 100 dB dB dB dB dB dB dB dB PLCC68 PSDIP64 80 75 dB dB equally weighted 20 Hz ... 16 kHz 3) (equally weighted 20 Hz ... 20 kHz) same signal source on left and right disturbing channel, channel effect on each observed output channel 2) 3) 3) Crosstalk between Main and AUX Output pairs DSP DACp1) PLCC68 PSDIP64 95 90 dB dB (equally weighted 20 Hz ... 16 kHz)3) same signal source on left and right disturbing channel, effect on each observed output channel (equally weighted 20 Hz ... 20 kHz) same signal source on g left and right disturbing channel, effect on each observed output channel Crosstalk from Main or AUX Output to SCART Output and vice versa D = disturbing program O = observed program D: MONO/SCn_IN/DSP SCn_OUT O: DSP DACp1) D: MONO/SCn_IN/DSP SCn_OUT O: DSP DACp1) D: DSP DACp O: MONO/SCn_IN SCn_OUT1) D: DSP DACp O: DSP SCn_OUT1) 1) 2) 3) PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 PLCC68 PSDIP64 90 85 95 85 100 95 100 95 dB dB dB dB dB dB dB dB SCART output load resistance 10 k SCART output load resistance 30 k 3) "n" means "1", "2" or "3", "s" means "L" or "R", DSP measured at I2S-Output DSP Input at I2S-Input "p" means "M" or "A" MICRONAS INTERMETALL 61 MSP 3400C PRELIMINARY DATA SHEET Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions PSRR: rejection of noise on AHVSUP at 1 kHz PSRR AGNDC From analog Input to DSP AGNDC MONO_IN SCn_IN_s1) MONO_IN SCn_IN_s,1) SCn_OUT_s1) SCn_OUT_s1) DACp_s1) 80 69 dB dB From analog Input to SCART Output 74 dB From DSP to SCART Output From DSP to MAIN/AUX Output Sound IF Input Section DCVREFTOP RIFIN DC voltage at VREFTOP 70 80 dB dB VREFTOP 2.4 2.6 2.7 V VSUPANALOG = 5 V RLoad 10 M AGC = +20 dB AGC = +3 dB RLoad 10 M AVSUP = 5 V RLoad 10 M fsig = 1 MHz, Input Level = -2 dBr Input Level = -2 dBr fsig = 1 MHz, Input Level = -2 dBr Input Impedance ANA_IN1+, ANA_IN2+, ANA_IN- 1.5 10.5 2 14.1 2.5 17.6 kOhm DCANA_IN XTALKIF BWIF AGC DC voltage on IF inputs 1.3 1.5 1.7 V Crosstalk attenuation 40 t.b.d. - dB 3 dB Bandwidth AGC step width 10 t.b.d. - 0.85 - t.b.d. MHz dB 1) "n" means "1", "2" or "3", "s" means "L" or "R", "p" means "M" or "A" 62 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Overall Performance S/NFM FM input to Main/AUX/SCART Output DACp_s, SCn_OUT_s1) 70 - dB 1 FM-carrier 5.5 MHz, 50 s, 1 kHz, 40 kHz deviation; RMS, unweighted 0 to 15 kHz; full input range S/ND2MAC Signal to Noise ratio of D2MAC baseband signal on Main/AUX/ SCART outputs Total Harmonic Distortion + Noise of FM demodulated signal on Main/AUX/SCART output Total Harmonic Distortion + Noise of D2MAC baseband signal for Main/AUX/SCART output Tolerance of output voltage of FM demodulated signal TBD - dB THDFM - 0.3 % 1 FM-carrier 5.5 MHz, 1kHz, 50 s; 40 kHz deviation; full input range 2.12 kHz, Modulator input level = 0 dBref 1 FM-carrier, 50 s, 1 kHz 40 kHz deviation; RMS 2.12 kHz, Modulator input level = 0 dBref 1 FM-carrier 5.5 MHz, 50 s, Modulator input level = -14.6 dBref; RMS Modulator input level = -12 dB dBref; RMS THDD2MAC - 0.01 0.1 % dVFMOUT -1.5 +1.5 dB dVD2MACOUT Tolerance of output voltage of D2MAC baseband signal FM frequency response on Main/ AUX/SCART outputs, bandwidth 20 to 15000 Hz D2MAC frequency response on Main/AUX/SCART outputs, bandwidth 20 to 15000 Hz FM channel separation (Stereo) -1.5 +1.5 dB fRFM -1.0 +1.0 dB fRD2MAC -1.0 +1.0 dB SEPFM 50 dB 2 FM-carriers 5.5/5.74 MHz, 50 s, 1 kHz, 40 kHz deviation; RMS SEPD2MAC XTALKFM D2MAC channel separation (Stereo) FM crosstalk attenuation (Dual) 80 dB 80 dB 2 FM-carriers 5.5/5.74 MHz, 50 s, 1 kHz, 40 kHz deviation; RMS XTALKD2MAC 1) D2MAC crosstalk attenuation (Dual) "s" means "L" or "R", 80 dB "n" means "1", "2" or "3", "p" means "M" or "A" MICRONAS INTERMETALL 63 MSP 3400C 9. Application of the MSP 3400C PRELIMINARY DATA SHEET Tuner 2 IF 2 IN Signal GND IF 1 IN 10 F + 100 nF 18.432 3.3 100 MHz F nF + 0.1 pF +8.0 V Tuner 1 + + 10 F 10 F 50pF 50pF 50pF XTAL_IN (62) 21 XTAL_OUT (63) 20 Ana_IN1+ (58) 25 Ana_IN2+ (60) 23 Ana_IN- (59) 24 AGNDC (42) 42 VREFTOP (54) 29 28 (55) MONO_IN 330 nF AHVSS 330 nF 31 (52) SC1_IN_L 330 nF AHVSS 330 nF 34 (49) SC2_IN_L 330 nF AHVSS 330 nF 37 (46) SC3_IN_L 330 nF 35 (48) ASG2 DACA_R (25) 60 36 (47) SC3_IN_R 1 nF 1 nF 32 (51) ASG1 33 (50) SC2_IN_R DACA_L (26) 59 1 nF DACM_R (28) 57 52 (30) ASG3 30 (53) SC1_IN_R 1 nF DACM_L (29) 56 CAPL_M (40) 44 CAPL_A (46) 38 1F 1F MAIN 1F 1F HEADPHONE MSP 3400C 5V 11 (7) STANDBY Q SC1_OUT_L (37) 47 SC1_OUT_R (36) 48 100 22 F 100 22 F + + 5V DVSS DVSS 12 (6) ADR_SEL SC2_OUT_L (34) 50 9 (9) I2C-CL 8 (10) I2C-DA 1 (16) S_ID 68 (17) S_CL 3 (15) S_DA_IN 6 (12) I2S_WS 7 (11) I2S_CL 4 (14) I2S_DA_IN1 65 (20) I2S_DA_IN2 5 (13) I2S_DA_OUT 61 (24) RESETQ 45 (39) AHVSUP 67 (18) DVSUP 26 (57) AVSUP 66 (19) DVSS D_CTR_OUT0 (5) 13 D_CTR_OUT1 (4) 14 AUD_CL_OUT (1) 18 DMA_SYNC (64) 19 TESTEN (61) 22 43 (41) AHVSS 49 (35) VREF1 58 (27) VREF2 SC2_OUT_R (33) 51 100 22 F + 100 22 F + 100 nF + 10 F 100 nF AVSS 100 nF 5V 5V 27 (56) AVSS DVSS 8.0 V Note: Pin numbers refer to PLCC packages, pin numbers for PSDIP packages in brackets. not connected pins are 2,10,15,16,17,38,39,40,41,53,54,55,62,63,64 (2,3,8,21,22,23,31,32,43,44,45) 64 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C AMU, DMA 2386, and DMA 2381, it is recommended to use a clock inverter circuit, as shown below right, a minimum gain of 1.0 at 18.432 MHz and an output phase as specified in Fig. 10-2. 10. DMA Application Fig. 10-1 shows an example for the D2MAC application with the MSP 3400 or MSP 3400C. To obtain the optimal amplitude and phase conditions for the clock input of + 5 Volt 5K S_DATA 66 S_IDENT 64 S_CLOCK 67 open 9 S_DATA_IN 15 S_IDENT 8 S_CLOCK AMU 2481 DMA 2381 Software: SBS = 1 ACS = 1 ACF = 0 DCOF= 1 (addr. 204, 214) ACLK 65 S_Bus Slave_mode S_DATA_OUT 6 13 AUDIO_CLOCK 17 16 18.432 MHz 68 S_CL 1 nF 1 S_ID 3 S_DA_IN MSP 3400C C6... MSP 3410/00 TC15/F7 MODE_REG[0] = 1 Clock Inverter (see below) +2...3 V 18 AUD_CL_OUT 4.7 nF 19 DMA_SYNC Clock Inverter 65 ACLK 66 S_DATA 64 S_IDENT +5 V 100 nF DMA 2386 To DMA 2381/86 and AMU 2481 BC 848C 120 6k8 10 nF 82 3k8 Fig. 10-1: DMA application with MSP 3410 TC15 or F7 Note: Pin numbers refer to PLCC packages for DMA 2381 and MSP 3400C and to PSDIP package for AMU 2481 MICRONAS INTERMETALL 65 MSP 3400C PRELIMINARY DATA SHEET MSP Clock Output Clock Inverter Output typ. 20 ns at inverter output Timing window for the low to high edge at pin 17 of DMA 2381 (XTAL2) > 10 ns < 42 ns Fig. 10-2: Timing requirements for the clock signal at the DMA 2381 clock input In the following table, the input/output clock-specification of the D2MAC circuit is shown. Table 10-1: Clock input and output specification for MSPs MSP 3400C >C6 new Version XTAL_IN min (minimum amplitude) C input (after Reset) AUD_CL_OUT min with C load Rout (HF) typ. > 0.7 Vpp 22 pF > 1.2 Vpp 40 pF 150 MSP 3410/00 TC27 new Version > 0.7 Vpp 22 pF > 1.2 Vpp 40 pF 120 MSP 3410/00 TC15 actual Version > 0.7 Vpp 31 pF > 1.0 Vpp 43 pF 120 Table 10-2: Clock input and output specification for ICs connected to MSP DMA 2381 XTAL_IN min Clock-in min (minimal amplitude) C input 24 pF 10 pF with: Adr. 204,14=1 7pF 7pF > 0.7 Vpp DMA 2386 > 0.7 Vpp AMU2481 > 0.7 Vpp For the DMA_SYNC input specification of the MSP, please refer to page 54 "VDMAIL, VDMAIH." 66 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 11. MSP Application with External Clock If for some reason, e.g. to spare the cost of an additional crystal, the MSP receives the 18.432 MHz clock from an external source, for example from an other MSP, the following circuit can be used. For input/output specification see also Table 10-1. 18.432 MHz 62 63 MSP 3400C or MSP 3410B AUD_CL_OUT 18 10 nF 62 XTAL_IN MSP 3400C LV 63 XTAL_OUT Fig. 11-1: MSP 3400C with external clock 12. ADR Application 18.432 MHz 18.432 MHz Tuner (Sat) S_CL S_ID S_DA_IN ADR-Interface SI1C SI1I SI1D PI16 PI15 SO1C SO1I SO1D PI14 MSP 3400C (in I2S Slave Mode) I2S_CL I2S_WS I2S_DA_IN 2S_DA_OUT I DRP 3510A I2S-Interface MICRONAS INTERMETALL 67 MSP 3400C 13. I2S Bus in Master/Slave Configuration with Standby Mode In a master/slave application, both MSP, after power up and reset, will start as master by default. This means that before the slave MSP is set to slave-mode, relatively large current-pulses (~20 mA) in the I2S_CL and I2S_WS lines can cause some crackling noise during startup time, if the the MSP is demuted before the slave MSP is set to slave mode. These high current pulses are also possible, if the active I2S_CL and I2S_WS outputs of the master MSP are clipped by the correspondent inputs of the slave MSP, which is switched to standby mode. To avoid this, it is recommended, that the I2S-bus lines I2S_CL and I2S_WS are current-limited to about 5 mA with series resistors of about 390 (330...470 ). Fig. 13-1 depicts the recommended application circuit for two MSP 3410/00 or MSP 3400C, which are connected via I2S Bus in a master/slave configuration, and where the slave MSP can be switched in standby mode (+5 Volt power is switched off). PRELIMINARY DATA SHEET Standby control +5 V 18.432 MHz 18.432 MHz 62 63 I2S_DA_IN 14 18 DVSUP 13 I2S_DA_OUT 14 I2S_DA_IN 12 I2S_WS R C 11 I2S_CL 7 STANDBYQ 62 63 MSP 3410/00 MSP 3400C (master) I2S_DA_OUT 13 I2S_WS 12 MSP 3410/00 MSP 3400C (slave) I2S_CL 11 minimal corner frequency = 4 MHz with R = 390 (330-470 ) Fig. 13-1: I2S master/slave application 68 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C 15. APPENDIX B: Documentation History 1. Advance Information: "MSP 3400C Multistandard Sound Processor", Apr. 14, 1994, 6251-377-1AI. First release of the advance information. 2. MSP 3400C Data Sheet: "MSP 3400C Multistandard Sound Processor", Dec. 14, 1994, 6251-377-1PD. First release of the preliminary data sheet. 3. MSP 3400C Data Sheet: "MSP 3400C Multistandard Sound Processor", Oct. 6, 1996, 6251-377-2PD. Second release of the preliminary data sheet. Major changes: see Appendix A: Version C6 4. MSP 3400C Data Sheet: "MSP 3400C Multistandard Sound Processor", Dec. 8, 1997, 6251-377-3PD. Third release of the preliminary data sheet. Major changes: see Appendix A: Version C7 and C8 - new PQFP80 package 14. APPENDIX A: Technical Code History TC01 First Release, compatible with MSP3410 and MSP 3400. Date: June 1994. TC04 Emulator version for software development. Version B5 New Features: 1. Equalizer 2. Improved identification 3. Improved adaptive deemphasis Version C6 New Features: 1. Adjustable Stereo Basewidth Enlargement (SBE) and switchable Pseudo Stereo Effect (SBE) 2. New Channel Matrix Modes (Mono, Sum/Dif, etc) 3. New Audio Clock Output Driver 4. Fast mute (Volume) 5. Clipping mode (Volume) 6. Sub dB steps for Volume, Bass, Treble, Equalizer Version C7 New Features: 1. Balance, Bass, Treble and Loudness for Headphone output 2. Prescale for I2S1 and I2S2 inputs 3. Balance in dB units and linear mode 4. SCART volume in dB units and linear mode 5. Increased range for Bass/Treble Version C8 New Features: 1. Automatic Volume Control A.V.C. 2. Subwoofer Output alternatively with Headphone Output. MICRONAS INTERMETALL 69 MSP 3400C PRELIMINARY DATA SHEET 70 MICRONAS INTERMETALL PRELIMINARY DATA SHEET MSP 3400C MICRONAS INTERMETALL 71 MSP 3400C PRELIMINARY DATA SHEET MICRONAS INTERMETALL GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@intermetall.de Internet: http://www.intermetall.de Printed in Germany Order No. 6251-377-3PD All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery dates are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, MICRONAS INTERMETALL GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Reprinting is generally permitted, indicating the source. However, our prior consent must be obtained in all cases. 72 MICRONAS INTERMETALL End of Data Sheet Multimedia ICs MICRONAS Back to Summary Back to Data Sheets |
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